Semiconductor chip having a dense arrangement of contact terminals

Patent metadata

Field	Value
Publication number	US-10090251-B2
Application number	US-201514808798-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Jul 24, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a semiconductor body having an active device region;
one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region; and
a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip,
wherein a minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip, the minimum distance being a design requirement to prevent shorting due to solder bridging between adjacent contact terminals,
wherein one or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance.

2. The semiconductor chip of claim 1 , wherein the contact terminals are solder bumps or copper pillars.

3. The semiconductor chip of claim 1 , wherein the pitch is between 90% and 25% of the defined minimum distance.

4. The semiconductor chip of claim 3 , wherein the pitch is between 50% and 25% of the defined minimum distance.

5. The semiconductor chip of claim 1 , wherein the contact terminals in at least one of the groups provide redundant external signal connections to the semiconductor chip for carrying the same information.

6. The semiconductor chip of claim 1 , wherein the contact terminals in at least one of the groups provide redundant power or ground connections to the semiconductor chip.

7. The semiconductor chip of claim 1 , wherein the contact terminals in at least one of the groups provide test connections to the semiconductor chip which are used only during testing of the semiconductor chip.

8. The semiconductor chip of claim 1 , wherein the semiconductor chip includes a bus, and wherein the contact terminals in at least one of the groups provide external signal connections for different lines of the bus.

9. The semiconductor chip of claim 1 , wherein the contact terminals in at least one of the groups provide external signal connections to the semiconductor chip for carrying different bits of information at the same voltage level.

10. The semiconductor chip of claim 1 , wherein at least one of the pitches is nonuniform and a function of a voltage level permitted for the contact terminals in each group with a nonuniform pitch.

11. The semiconductor chip of claim 1 , wherein the semiconductor chip has an allowable contact terminal area for placement of the contact terminals, and wherein a total area consumed by the contact terminals exceeds 15% of the available contact terminal area.

12. A semiconductor chip, comprising:
a semiconductor body; and
a plurality of contact terminals spaced apart from the semiconductor body and configured to provide external electrical access to the semiconductor chip,
wherein a minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip, the minimum distance being a design requirement to prevent shorting due to solder bridging between adjacent contact terminals,
wherein at least some of the contact terminals have an electrical or functional commonality and a pitch which is less than the defined minimum distance.

13. The semiconductor chip of claim 1 , wherein some of the contact terminals have an irregular shape.

Assignees

• Infineon Technologies Ag

Inventors

• Ossimitz Peter
• Beer Gottfried
• Hoegerl Juergen
• Munding Andreas

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W72/237

  Multiple bump connectors having different shapes · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title