System and method for dual-region singulation

Patent metadata

Field	Value
Publication number	US-10090215-B2
Application number	US-201715403673-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Mar 17, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.

First claim

What is claimed is:

1. A semiconductor die comprising:
a semiconductor circuit disposed within or over a substrate;
a conductive contact pad disposed over the substrate outside the semiconductor circuit; and
a electrical path ending at a singulated edge of the die, wherein the electrical path is electrically coupled to the conductive contact pad without being electrically coupled to the semiconductor circuit.

2. The semiconductor die of claim 1 , wherein the electrical path comprises a polysilicon path.

3. The semiconductor die of claim 1 , wherein the electrical path comprises a substrate material of the semiconductor circuit.

4. The semiconductor die of claim 1 , wherein the electrical path comprises aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, or a metal nitride.

5. The semiconductor die of claim 1 , wherein the conductive contact pad comprises aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, or a metal nitride.

6. The semiconductor die of claim 1 , wherein the semiconductor circuit comprises a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar transistor, an insulated-gate bipolar transistor (IGBT), a diode, a sensor, or an integrated circuit.

7. A semiconductor die comprising:
an active region comprising a semiconductor circuit disposed within or over a substrate;
a seal-ring surrounding the active region;
a pad region disposed on one side of the seal-ring outside the active region;
a plurality of conductive contact pads disposed in the pad region; and
a plurality of electrical paths ending at a singulated edge of the die, wherein each of the plurality of electrical paths extend from a contact pad of the plurality of conductive contact pads without being electrically coupled to the semiconductor circuit.

8. The semiconductor die of claim 7 , wherein the plurality of electrical paths comprises polysilicon wires.

9. The semiconductor die of claim 7 , wherein the plurality of electrical paths comprises a substrate material of the substrate.

10. The semiconductor die of claim 7 , wherein the plurality of electrical paths comprises aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, or a metal nitride.

11. The semiconductor die of claim 7 , wherein the plurality of conductive contact pads comprises aluminum, copper, titanium, tungsten, cobalt, platinum, palladium, molybdenum, nickel, vanadium, silver, gold, aluminum, a metal silicide, or a metal nitride.

12. The semiconductor die of claim 7 , wherein the semiconductor circuit comprises a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar transistor, an insulated-gate bipolar transistor (IGBT), a diode, a sensor, or an integrated circuit.

13. The semiconductor die of claim 7 , wherein the plurality of conductive contact pads comprises surface contact pads and buried contact pad.

14. The semiconductor die of claim 7 , wherein the seal-ring comprises a crack stop region that includes a gap on an uppermost insulating layer of the substrate.

15. A semiconductor die comprising:
an active region comprising a semiconductor circuit disposed within or over a substrate;
a seal-ring surrounding the active region;
a first pad region disposed on a first side of the seal-ring outside the active region;
a second pad region disposed on a second side of the seal-ring outside the active region;
a first plurality of conductive contact pads disposed in the first pad region; and
a first plurality of electrical paths ending at a first edge of the semiconductor die, wherein each of the first plurality of electrical paths extend from a contact pad of the first plurality of conductive contact pads without being electrically coupled to the semiconductor circuit;
a second plurality of conductive contact pads disposed in the second pad region; and
a second plurality of electrical paths ending at a second edge of the semiconductor die, wherein each of the second plurality of electrical paths extend from a contact pad of the second plurality of conductive contact pads without being electrically coupled to the semiconductor circuit.

16. The semiconductor die of claim 15 , wherein the first side intersects with the second side.

17. The semiconductor die of claim 15 , wherein the first plurality of electrical paths extend in a first direction away from the first plurality of conductive contact pads, wherein the second plurality of electrical paths extend in a second direction away from the second plurality of conductive contact pads, and wherein the first direction is perpendicular to the second direction.

18. The semiconductor die of claim 15 , wherein the first and the second plurality of electrical paths comprises polysilicon wires.

19. The semiconductor die of claim 15 , wherein the first and the second plurality of electrical paths comprises silicon.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Wood Andrew Christopher Graeme
• Fasching Gernot
• Bodea Marius Aurel
• Ostermann Thomas Krotscheck
• Bacher Erwin

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title