Performing logical operations using sensing circuitry

Patent metadata

Field	Value
Publication number	US-10090041-B2
Application number	US-201715680776-A
Country	US
Kind code	B2
Filing date	Aug 18, 2017
Priority date	Jun 5, 2014
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Apparatuses and methods related to performing logical operations using sensing circuitry are provided. One apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.

First claim

What is claimed is:

1. A system, comprising:
a host; and
a memory device coupled to the host and comprising an array of memory cells and corresponding sensing circuitry configured to perform logical operations between operands stored in memory cells corresponding to a same column and coupled to different access lines, without transferring the operands to the host, by using the array as an accumulator.

2. The system of claim 1 , wherein the host comprises a processor external to the memory device, and wherein the memory device comprises a processor in memory device.

3. The system of claim 1 , wherein the memory device comprises a controller coupled to the array and to the sensing circuitry.

4. The system of claim 1 , wherein the memory device is configured to perform at least one logical operation by copying a data value corresponding to a first operand stored in a memory cell and coupled to a first access line into two different memory cells coupled to respective different access lines by simultaneously activating the respective different access lines.

5. The system of claim 1 , wherein the memory device is configured to perform a logical operation between a first operand stored in a first memory cell coupled to a first access line and a second operand stored in a second memory cell coupled to a second access line by modifying a voltage of a sense line corresponding to the column to an extent that a charge of the second memory cell storing the second operand is not sufficient to change a data value represented by the modified voltage of the sense line.

6. The system of claim 1 , wherein the memory device is configured to perform a logical operation between a first operand stored in a first memory cell coupled to a first access line and a second operand stored in a second memory cell coupled to a second access line by:
applying, to a plurality of access lines, a voltage:
sufficient to cause access devices coupled thereto to be turned-on responsive to memory cells to which the access devices correspond storing a particular data value; and
insufficient to cause the access devices coupled thereto to be turned-on responsive to memory cells of the array to which the access devices correspond storing a different particular data value; and

coupling a memory cell storing a charge corresponding to the first operand to a sense line corresponding to the column after applying the voltage to the plurality of access without performing an equilibration operation after applying the voltage to the plurality of access lines.

7. The system of claim 1 , wherein the array comprises DRAM cells.

8. The system of claim 1 , wherein the memory device is configured to perform at least one logical operation between operands stored in memory cells corresponding to a same column and coupled to different access lines by:
storing a first charge corresponding to a first operand of the logical operation in a plurality of memory cells corresponding to the column;
charging access lines corresponding to the plurality of the memory cells to a voltage to which a sense line corresponding to the column is charged plus some portion of a threshold voltage of a memory cell access device;
isolating the plurality of memory cells from the sense line;
coupling of a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line; and
sensing of a voltage of the sense line to yield a result of the logical operation.

9. A system, comprising:
a host; and
a memory device coupled to the host and configured to perform a logical operation between a first operand stored in a memory cell of an array and a second operand stored in a memory cell of the array without transferring the operands to the host by:
charging multiple access lines corresponding to the array to within a voltage to which a sense line is charged plus some portion of a threshold voltage of a memory cell access device coupled to the sense line and to one of the multiple access lines; and
modifying the sense line voltage with a charge stored in a memory cell coupled to the sense line and to an access line other than the multiple access lines, the charge stored in the memory cell corresponding to one of the first operand and the second operand of the logical operation, the modified voltage of the sense line indicating a result of the logical operation.

10. The system of claim 9 , wherein the memory device comprises a processing in memory device, and wherein the host is external to the memory device.

11. The system of claim 9 , wherein the array is used as an accumulator in association with performing the logical operation.

12. The system of claim 9 , wherein the first and second memory cells are coupled to different access lines and correspond to a same column of the array.

13. The system of claim 12 , wherein the sense line is one of a pair of complementary sense lines corresponding to the same column.

14. The system of claim 9 , wherein the memory device is configured to perform the logical operation by equilibrating the sense line to an equilibrate voltage prior to charging the multiple access lines, wherein charging the multiple access lines includes charging the multiple access lines to the equilibrate voltage.

15. The system of claim 9 , wherein the memory device is configured to perform the logical operation by equilibrating the sense line to about one half of a supply voltage prior to charging the multiple access lines, wherein charging the multiple access lines includes charging the multiple access lines to about one half of the supply voltage.

16. The system of claim 9 , wherein the memory device is configured to perform the logical operation by charging the multiple access lines to a voltage within a range from the threshold voltage of the memory cell access device to the threshold voltage of the memory cell access device plus a voltage to which the sense line is charged.

17. The system of claim 9 , wherein the memory device is configured to perform the logical operation by charging the different access lines to a voltage within a range from the threshold voltage of the memory cell access device to the threshold voltage of the memory cell access device plus a sense line equilibration voltage.

18. A method, comprising:
receiving, at a memory device, instructions from a host; and
executing the instructions on the memory device, wherein executing the instructions comprises performing at least one logical operation between operands stored in memory cells corresponding to a same column and coupled to different access lines of an array, without transferring the operands to the host, by using the array as an accumulator.

19. The method of claim 18 , wherein performing the at least one logical operation comprises:
storing a first charge corresponding to a first operand of the at least one logical operation to a plurality of memory cells corresponding to the same column;
charging access lines coupled to the plurality of the memory cells to a voltage to which a sense line corresponding to the same column is charged plus some portion of a threshold voltage of a memory cell access device;
isolating the plurality of memory cells from the sense line;
coupling a memory cell storing a charge corresponding to a second operand of the at least one logical operation to one of the sense line and a complementary sense line corresponding to the same column; and
sensing a voltage of the sense line to determine a result of the at least one logical operation.

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Assignees

• Micron Technology Inc
• Micro Tech Inc

Inventors

• Hush Glen E

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title