Intelligent cell swapping based on ceiling determination, floor determination, and cell attribute weighting criteria

Patent metadata

Field	Value
Publication number	US-10089428-B2
Application number	US-201514981848-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	May 4, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Embodiments of the inventive concept include a computer-implemented method for intelligently swapping circuit cells and an associated intelligent cell swapper logic section. The technique can include receiving, by an intelligent cell swapper logic section, a synthesized gate level netlist including cells each having an initial cell class. A cell class sorter can sort cell classes in order of leakage. A ceiling finder can swap the initial cell class for each of the cells to a highest cell leakage class, and determine a ceiling frequency. A floor finder can swap the highest cell leakage class for each of the cells to a lowest cell leakage class, and determine a floor frequency. An effective swap weight calculator section can determine an effective swap weight for a subset of cells based on cell attribute weighting criteria. The timing paths can be optimized to meet the ceiling frequency without unnecessarily using high leakage cells.

First claim

What is claimed is:

1. A computer-implemented method for intelligently swapping circuit cells, comprising:
receiving, by an intelligent cell swapper logic section, a synthesized gate level netlist including a design having a plurality of cells each having an initial cell leakage class;
sorting, by a cell class sorter, a plurality of cell classes in order of leakage;
swapping, by a ceiling finder, the initial cell leakage class for each of the plurality of cells to a highest cell leakage class from among the plurality of cell classes;
determining a ceiling frequency of the design, wherein determining the ceiling frequency of the design includes determining a maximum obtainable frequency associated with the synthesized gate level netlist;
swapping, by a floor finder, the highest cell leakage class for each of the plurality of cells to a lowest cell leakage class from among the plurality of cell classes;
determining a floor frequency of the design, wherein determining the floor frequency of the design includes determining a lowest leakage the design can achieve associated with the synthesized gate level netlist;
generating, by a timing path list creator, a list of a plurality of timing paths, associated with the plurality of cells, that do not meet the ceiling frequency of the design;
sorting, by a slack value sorting section, the list of the plurality of timing paths in order of slack values;
initializing, by a swapped cell list initializer, a swapped cell list;
creating, by a cell list creator, a cell list including a subset of the plurality of cells for a particular timing path from among the plurality of timing paths; and
updating a current cell class, to an updated cell class, of any previously swapped cells associated with the swapped cell list that are within the subset of the plurality of cells associated with the particular timing path.

2. The computer-implemented method of claim 1 , further comprising:
updating, by a slack updater, a slack on the particular timing path;
determining whether first criteria are met; and
in response to determining that the first criteria are met, determining, by an effective swap weight calculator section, an effective swap weight for each cell that is part of the subset of the plurality of cells associated with the particular timing path.

3. The computer-implemented method of claim 2 , further comprising:
reordering, by an effective swap weight reorder section, the subset of the plurality of cells associated with the particular timing path in order of the effective swap weight; and
swapping, by a cell swapper, a cell class of a cell having a highest effective swap weight from among the reordered subset of the plurality of cells, with a new cell class from among the plurality of cell classes.

4. The computer-implemented method of claim 3 , further comprising:
storing, in the swapped cell list, the new cell class of the cell.

5. The computer-implemented method of claim 4 , further comprising:
after swapping and storing, updating, by the slack updater, the slack on the particular timing path;
determining whether second criteria are met;
in response to determining that the second criteria are met, determining whether third criteria are met; and
in response to determining that the third criteria are met, recalculating, by the effective swap weight calculator section, an effective swap weight for the cell having the new cell class.

6. The computer-implemented method of claim 5 , further comprising:
in response to determining that the third criteria are not met, removing the cell having the new class from consideration.

7. The computer-implemented method of claim 5 , wherein the particular timing path is referred to as a first particular timing path, the method further comprising:
in response to determining that the second criteria are not met, incrementing, by an iteration section, an index of the list of the plurality of timing paths, thereby selecting a second particular timing path for evaluation.

8. The computer-implemented method of claim 7 , wherein the cell list is referred to as a first cell list, and the subset is referred to as a first subset, the method further comprising:
determining whether fourth criteria are met; and
in response to determining that the fourth criteria are met, creating, by the cell list creator, a second cell list including a second subset of the plurality of cells for the second particular timing path from among the plurality of timing paths,
wherein the first criteria includes whether or not the slack on the particular timing path meets the ceiling frequency of the design;
wherein the second criteria includes whether or not the slack on the particular timing path meets the ceiling frequency of the design;
wherein the third criteria includes whether or not a cell leakage class index is less than a number of defined leakage classes for a given cell of the cell list; and
wherein the fourth criteria includes whether or not the index of the list of the plurality of timing paths is less than a total number of timing paths.

9. An intelligent cell swapper, comprising:
an intelligent cell swapper logic section configured to receive a synthesized gate level netlist including a design having a plurality of cells each having an initial cell leakage class;
a cell class sorter configured to sort a plurality of cell classes in order of leakage;
a ceiling finder configured to swap the initial cell leakage class for each of the plurality of cells to a highest cell leakage class from among the plurality of cell classes, wherein the ceiling finder is configured to determine a ceiling frequency of the design by at least determining a maximum obtainable frequency associated with the synthesized gate level netlist; and
a floor finder configured to swap the highest cell leakage class for each of the plurality of cells to a lowest cell leakage class from among the plurality of cell classes, wherein the floor finder is configured to determine a floor frequency of the design by at least determining a lowest leakage the design can achieve associated with the synthesized gate level netlist;
a timing path list creator configured to generate a list of a plurality of timing paths, associated with the plurality of cells, that do not meet the highest frequency of the design;
a slack value sorting section configured to sort the list of the plurality of timing paths in order of slack values;
a swapped cell list initializer configured to initialize a swapped cell list;
a cell list creator configured to create a cell list including a subset of the plurality of cells for a particular timing path from among the plurality of timing paths; and
a cell updater configured to update a current cell class, to an updated cell class, of any previously swapped cells associated with the swapped cell list that are within the subset of the plurality of cells associated with the particular timing path.

10. The intelligent cell swapper of claim 9 , further comprising:
a slack updater configured to update a slack on the particular timing path; and
an effective swap weight calculator section configured to determine an effective swap weight for each cell that is part of the subset of the plurality of cells associated with the particular timing path.

11. The intelligent cell swapper of claim 10 , further comprising:
an effective swap weight reorder section configured to reorder the subset of the plurality of cells associated with the particular timing path in order of the effective swap weight; and
a cell swapper configured to swap a cell class of a cell having the highest effective swap weight from among the reordered subset of th

Assignees

• Chowdhury Ahsan H
• Colyer Robert A
• Fedor John M
• Millar Brian
• Kwon Yohan
• Samsung Electronics Co Ltd

Inventors

• Chowdhury Ahsan H
• Colyer Robert A
• Fedor John M
• Millar Brian
• Kwon Yohan

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F17/5068 Primary

  Physics · mapped topic

• G06F17/505

  Physics · mapped topic