Systems and methods for interleaved coded modulation with convolutional coding-based low-density parity check codes

Patent metadata

Field	Value
Publication number	US-10084482-B2
Application number	US-201615190137-A
Country	US
Kind code	B2
Filing date	Jun 22, 2016
Priority date	Jun 22, 2015
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Various apparatus and methods may use iterative de-mapping/decoding to on received symbol estimates corresponding to interleaved coded modulation (ICM) using low-density parity check convolutional coding (LPDC-CC). The iterative de-mapping/decoding, may take the form of a multi-stage feed-forward arrangement that may include multiple identically designed stages, and the stages may use parallelism to increase speed and efficiency.

First claim

What is claimed is:

1. A communication apparatus, including:
a receiver that receives optical signals, the receiver having an optical hybrid circuit and a local oscillator laser, the optical hybrid circuit mixing at least portions of the received optical signals with light supplied by the local oscillator laser, the receiver outputting first electrical signals;
a digital signal processor coupled to the receiver, the digital signal process outputting second electrical signals based on the first electrical signals;
a symbol de-interleaver coupled to the digital signal processor, the symbol de-interleaver supplying third electrical signals based on the second electrical signals,
a multi-stage feed-forward iterative decoder that receives the third electrical signals, comprising at least two stages, wherein a respective one of the at least two stages includes:
an M-ary soft-decision symbol de-mapper configured to de-map received symbol estimates and to output soft decision data corresponding to one or more respective bits corresponding to a given symbol; and
a low-density parity check convolutional code (LDPC-CC) decoder configured to input the soft-decision data and to combine the soft-decision data with extrinsic decoding information, to compute a running summation of extrinsic decoding information computed within the LDPC-CC decoder, and to output further soft-decision data and extrinsic decoding information computed within the LDPC-CC decoder.

2. The communication apparatus of claim 1 , further including:
a hard decision device configured to receive soft-decision data from an output of a last of the at least two stages and to output bit values.

3. The communication apparatus of claim 1 , wherein the soft-decision data and further soft-decision data are log-likelihood ratio values for respective bits corresponding to the symbol estimates.

4. The communication apparatus of claim 1 , wherein the de-mapper of at least one of the at least two stages is enabled to be deactivated or bypassed, and wherein the soft-decision data input to the LDPC-CC decoder corresponds to soft-decision data input to the at least one of the at least two stages.

5. The communication apparatus of claim 1 , wherein the outputs of a given stage of the at least two stages include the symbol estimates and the further soft-decision data, and the extrinsic decoding information.

6. The communication apparatus of claim 5 , wherein the outputs of the given stage are passed as inputs to a next stage of the at least two stages.

7. The communication apparatus of claim 5 , wherein the symbol estimates and the soft-decision data, and the extrinsic decoding information comprise multiple values and are passed in parallel.

8. The communication apparatus of claim 1 , wherein a respective stage further includes a symbol buffer configured to delay the symbol estimates.

9. The communication apparatus of claim 1 , wherein the LDPC-CC decoder comprises a min-sum decoder architecture with parallel branches corresponding to respective constraints of the LDPC-CC decoder.

10. The communication apparatus of claim 1 , wherein the de-mapper is configured to compute the soft-decision data using Euclidean distances of symbols from constellation points of modulation used to transmit symbols to the communication apparatus, adjusted by soft-decision data input to the de-mapper from a previous stage, wherein the soft-decision data input to a first stage of the at least two stages is zero for all bits.

11. A method in a communications receiver, the method including:
receiving optical signals optical signals with an optical receiver;
mixing at least portions of the received optical signals with light supplied by a local oscillator laser;
outputting, with the optical receiver, first electrical signals based on the received optical signals;
outputting, with a digital signal processor coupled to the receiver, second electrical signals based on the first electrical signals;
outputting, with a symbol de-interleaver coupled to the digital signal processor, third electrical signals based on the second electrical signals;
performing multi-stage iterative feed-forward decoding based on the third electrical signals, said performing multi-stage iterative feed-forward decoding comprising:
performing a first de-mapping of symbol estimates and outputting soft-decision bit data for one or more bits corresponding to the symbol estimates;
performing a first low-density parity check convolutional code (LDPC-CC) decoding based on the soft-decision bit data, using extrinsic decoding information, to output further soft-decision data for the one or more bits corresponding to the symbol estimates and further extrinsic decoding information computed during the LDPC-CC decoding;

performing a first maintaining of running parallel sums of the further extrinsic decoding information; and
performing one or more further iterations of de-mapping M-ary symbol estimates, LDPC-CC decoding, and maintaining the running parallel sums based at least in part on outputs of the first de-mapping and the first LDPC-CC decoding.

12. The method of claim 11 , further including:
making hard decisions based on soft-decision data from an output of a last of the one or more further iterations and outputting resulting bit values from the hard decisions.

13. The method of claim 11 , wherein the soft-decision bit data and further soft-decision bit data are log-likelihood ratio values for respective bits corresponding to the symbol estimates.

14. The method of claim 11 , wherein the performing one or more further iterations comprises, in at least one of the one or more further iterations, bypassing the de-mapping M-ary symbol estimates, wherein the soft-decision bit data input to the LDPC-CC decoding of the at least one of the one or more further iterations, in which the de-mapping is bypassed, corresponds to soft-decision data input to the at least one of the one or more further iterations.

15. The method of claim 11 , wherein the outputs of the performing the first de-mapping, performing the first LDPC-CC decoding, and performing the first maintaining, as well as the outputs of the one or more further iterations, include the symbol estimates, the further soft-decision data, extrinsic decoding information resulting from, in the case of the first de-mapping and first-LDPC-CC decoding, as well as in the case of the de-mapping and LDPC-CC decoding of the one or more further iterations.

16. The method of claim 15 , wherein the symbol estimates, the soft-decision data, and the extrinsic decoding information comprise multiple values and are output in parallel.

17. The method of claim 11 , wherein the performing the first LDPC-CC decoding and the LDPC-CC decoding of the one or more further iterations comprise performing min-sum decoding with parallel branches corresponding to respective constraints of the LDPC-CC decoding.

18. The method of claim 11 , wherein the first de-mapping and the de-mapping of the one or more further iterations comprises:
computing the soft-decision data using Euclidean distances of symbols from constellation points of a modulation type used to transmit the symbols, adjusted by soft-decision data input to the de-mapping from a previous iteration, wherein the soft-decision data input to the first de-mapping is zero for all bits.

19. A non-transitory computer-readable medium containing executable code configured to cause at least one processing device to perform operations including:
outputting, with a digital signal processor

Assignees

• Infinera Corp

Inventors

• Karar Abdullah
• Sun Han Henry
• Wu Kuang-Tsan

Classifications

• H03M13/1122

  storing only the first and second minimum values per check node · CPC title

• H03M13/2957

  Turbo codes and decoding · CPC title

• H03M13/1154 Primary

  Low-density parity-check convolutional codes [LDPC-CC] · CPC title

• H03M13/6325

  Error control coding in combination with demodulation · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title