Frequency synthesizer with tunable accuracy

Patent metadata

Field	Value
Publication number	US-10084457-B2
Application number	US-201715408655-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Jan 18, 2017
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.

First claim

The invention claimed is:

1. An apparatus comprising:
a first circuit configured to generate a first code by counting a number of cycles of an input clock signal during a period, wherein (a) said period is determined by (i) an output clock signal and (ii) a second code, and (b) said second code (i) is read from a memory internal to said first circuit and (ii) has a variable multi-bit value;
a second circuit configured to generate a third code by a delta-sigma modulation of said first code; and
a third circuit configured to generate said output clock signal (i) in response to said third code and (ii) within a frequency accuracy determined by a current value of said second code.

2. The apparatus according to claim 1 , wherein said first circuit is further configured to adjust said second code to change a duration of said period.

3. The apparatus according to claim 1 , wherein said first circuit is further configured to set said second code to an initial value that establishes a short duration of said period in which a frequency of said output clock signal is adjusted to a coarse accuracy.

4. The apparatus according to claim 3 , wherein said coarse accuracy is achieved when said number of cycles of said input clock during said period minus an expected number falls below a threshold.

5. The apparatus according to claim 3 , wherein said first circuit is further configured to set said second code to a subsequent value that establishes a long duration of said period in which said frequency of said output clock signal is adjusted to a fine accuracy.

6. The apparatus according to claim 5 , wherein said first circuit is further configured to repeat said short duration at most a given number of times before using said subsequent value.

7. The apparatus according to claim 1 , wherein said second circuit is further configured to parse said first code into an integer value and a fractional value.

8. The apparatus according to claim 7 , wherein said delta-sigma modulation is applied to said fractional value to generate a fine adjustment value.

9. The apparatus according to claim 8 , wherein said third code is generated in said second circuit by adding said fine adjustment value to said integer value.

10. The apparatus according to claim 1 , wherein said first circuit is further configured to vary a power consumption of said apparatus based on said second code by alternately enabling and disabling a clock generator from generating said input clock signal.

11. A method for frequency synthesization, comprising the steps of:
generating a first code using a circuit by counting a number of cycles of an input clock signal during a period, wherein (a) said period is determined by (i) an output clock signal and (ii) a second code, and (b) said second code is (i) read from a memory internal to said circuit and (ii) has a variable multi-bit value;
generating a third code by a delta-sigma modulation of said first code; and
generating said output clock signal (i) in response to said third code and (ii) within a frequency accuracy determined by a current value of said second code.

12. The method according to claim 11 , further comprising the step of:
adjusting said second code to change a duration of said period.

13. The method according to claim 11 , further comprising the step of:
setting said second code to an initial value that establishes a short duration of said period in which a frequency of said output clock signal is adjusted to a coarse accuracy.

14. The method according to claim 13 , wherein said coarse accuracy is achieved when said number of cycles of said input clock during said period minus an expected number falls below a threshold.

15. The method according to claim 13 , further comprising the step of:
setting said second code to a subsequent value that establishes a long duration of said period in which said frequency of said output clock signal is adjusted to a fine accuracy.

16. The method according to claim 15 , further comprising the step of:
repeating said short duration at most a given number of times before using said subsequent value.

17. The method according to claim 11 , further comprising the step of:
parsing said first code into an integer value and a fractional value.

18. The method according to claim 17 , wherein said delta-sigma modulation is applied to said fractional value to generate a fine adjustment value.

19. The method according to claim 18 , wherein said third code is generated by adding said fine adjustment value to said integer value.

20. The method according to claim 11 , further comprising the step of:
varying a power consumption based on said second code by alternately enabling and disabling a clock generator from generating said input clock signal.

Assignees

• Integrated Device Tech

Inventors

• Li Hui
• Ng Teck-Chuan
• Aycock Stephen E

Classifications

• H03M3/39

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title

• H03K21/02 Primary

  Input circuits · CPC title