Auto frequency calibration method

Patent metadata

Field	Value
Publication number	US-9838024-B2
Application number	US-201615341183-A
Country	US
Kind code	B2
Filing date	Nov 2, 2016
Priority date	Apr 20, 2012
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.

First claim

What is claimed is:

1. A method of generating an output signal, the method comprising:
determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal;
determining a first logic value of a control signal by a comparing circuit based on the sampling period N; and
generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal, wherein
when an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.

2. The method of claim 1 , further comprising:
generating a fine tuning signal by a digital loop filter based on the phase difference signal.

3. The method of claim 2 , further comprising:
adjusting an output frequency of the output signal by a voltage controlled oscillator based on the coarse tuning signal and the fine tuning signal.

4. The method of claim 1 , further comprising:
determining if (M+1) LSB equals the second logic value when the M-th LSB of the number of MSBs of the divider number control signal does not equal the second logic value.

5. The method of claim 1 , wherein determining the sampling period N according to the number of MSBs of the divider number control signal comprises:
determining the sampling period N according to a divisor ratio signal received from a delta-sigma modulator.

6. The method of claim 1 , wherein determining the sampling period N according to the number of MSBs of the divider number control signal comprises:
determining a fractional portion of a divisor ratio signal received from a delta-sigma modulator; and
determining the sampling period N based on the number of MSBs of the fractional portion of the divisor ratio signal.

7. The method of claim 6 , wherein determining the sampling period N based on the number of MSBs of the fractional portion of the divisor ratio signal is performed by a look-up table.

8. The method of claim 1 , further comprising:
generating the phase difference signal by a phase difference detector based on a reference frequency and a divider frequency.

9. The method of claim 8 , wherein generating the phase difference signal by the phase difference detector based on the reference frequency and the divider frequency comprises:
when the reference frequency leads the divider frequency,
generating the coarse tuning signal by the code generating circuit to increase an output frequency of the output signal; and

when the reference frequency does not lead the divider frequency,
generating the coarse tuning signal by the code generating circuit to decrease the output frequency of the output signal.

10. The method of claim 1 , wherein determining the first logic value of the control signal by the comparing circuit based on the sampling period N comprises:
comparing the sampling period N with a counter signal generated by a counter,
when the sampling period N equals the counter signal, the comparing circuit outputs the first logic value of the control signal.

11. A method of generating an output signal, the method comprising:
generating a phase difference signal by a phase difference detector based on a reference frequency and a divider frequency;
determining a first logic value of a control signal by a comparing circuit based on a sampling period N;
generating a coarse tuning signal by a code generating circuit based on the phase difference signal and the first logic value of the control signal; and
adjusting an output frequency of the output signal based on the coarse tuning signal, wherein
the sampling period N is determined according to a number of most significant bits (MSBs) of a divider number control signal.

12. The method of claim 11 , further comprising:
when an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value,
setting the sampling period N based on the M-th LSB of the number of MSBs of the divider number control signal.

13. The method of claim 11 , wherein adjusting the output frequency of the output signal based on the coarse tuning signal comprises:
generating a fine tuning signal by a digital loop filter based on the phase difference signal; and
adjusting the output frequency of the output signal by a voltage controlled oscillator based on the coarse tuning signal and the fine tuning signal.

14. The method of claim 11 , wherein determining the first logic value of the control signal by the comparing circuit based on a sampling period N comprises:
comparing the sampling period N with a counter signal generated by a counter; and
when the sampling period N equals the counter signal,
outputting the first logic value of the control signal.

15. The method of claim 11 , wherein adjusting the output frequency of the output signal based on the coarse tuning signal comprises:
when the reference frequency leads the divider frequency,
generating the coarse tuning signal by the code generating circuit to increase the output frequency of the output signal; and

when the reference frequency does not lead the divider frequency,
generating the coarse tuning signal by the code generating circuit to decrease the output frequency of the output signal.

16. A method of generating an output signal, the method comprising:
generating a phase difference signal by a phase difference detector based on a reference frequency and a divider frequency;
generating a coarse tuning signal by a code generating circuit based on the phase difference signal and a first logic value of a control signal;
generating a fine tuning signal by a digital loop filter based on the phase difference signal; and
adjusting an output frequency of the output signal based on the coarse tuning signal and the fine tuning signal, wherein
the first logic value of the control signal is determined based on a sampling period N, and
the sampling period N is determined according to a number of most significant bits (MSBs) of a divider number control signal.

17. The method of claim 16 , wherein generating the phase difference signal by the phase difference detector based on the reference frequency and the divider frequency comprises:
determining whether the reference frequency leads the divider frequency.

18. The method of claim 17 , wherein adjusting the output frequency of the output signal based on at least the coarse tuning signal comprises:
when the reference frequency leads the divider frequency,
generating the coarse tuning signal by the code generating circuit to increase the output frequency of the output signal; and

when the reference frequency does not lead the divider frequency,
generating the coarse tuning signal by the code generating circuit to decrease the output frequency of the output signal.

19. The method of claim 16 , further comprising:
when an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value,
setting the sampling period N based on the M-th LSB of the number of MSBs of the divider number control signal; and

when the M-th LSB of the number of MSBs of the divider number control signal does not equal the second logic value,
determining if (M+1) LSB equals the second logic value.

20. The method of claim 16 , wherein generating the coarse tuning signal by the code generating circuit based on the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yen-Jen
• Kuo Feng Wei
• Chen Huan-Neng
• Jou Chewn-Pu

Classifications

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title