Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10083978-B2
Application number	US-201815867974-A
Country	US
Kind code	B2
Filing date	Jan 11, 2018
Priority date	Aug 24, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first gate structures on a substrate, each of the first gate structures having a first width;
second gate structures on the substrate, each of the second gate structures having a second width greater than the first width;
first capping insulation patterns covering upper portions of the first and second gate structures, a first opening being between neighboring ones of the second gate structures;
first spacer structures on sidewalls of each of the second gate structures and each of the first capping insulation patterns that are exposed by the first opening, each of the first spacer structures including a first spacer and a second spacer; and
a first impurity region at an upper portion of the substrate between the first spacer structures.

2. The semiconductor device of claim 1 , wherein the first spacer includes a material different from a material of the second spacer.

3. The semiconductor device of claim 1 , wherein the first spacer is on the sidewalls of each of the second gate structures and each of the first capping insulation patterns and an upper surface of the substrate, the first spacer including a curved portion between the second gate structure and the upper surface of the substrate.

4. The semiconductor device of claim 3 , wherein the second spacer is on the first spacer.

5. The semiconductor device of claim 1 , wherein the first capping insulation patterns do not fill a space between the first gate structures, so that an air gap is defined by the space between the first gate structures.

6. The semiconductor device of claim 1 , wherein each of the first and second gate structures includes a gate insulation layer, a first conductive pattern, a dielectric pattern, a second conductive pattern and a third conductive pattern sequentially stacked.

7. The semiconductor device of claim 6 , wherein the first, second and third conductive patterns in each of the second gate structures are electrically connected to each other.

8. The semiconductor device of claim 6 , wherein the third conductive patterns in the first and second gate structures include a metal or a metal nitride.

9. The semiconductor device of claim 1 , wherein each of the first and second gate structures includes a gate insulation layer, a charge trapping pattern, a dielectric pattern and a conductive pattern sequentially stacked.

10. The semiconductor device of claim 1 , wherein an upper width of the first opening is greater than a lower width of the first opening, and a sidewall of each of the first capping insulation patterns has an inflection point.

11. The semiconductor device of claim 1 , further comprising:
a third gate structure on the substrate, the third gate structure having a third width greater than the second width;
a second capping insulation pattern on the third gate structure; and
a second spacer structure on sidewalls of the third gate structure and the second capping insulation pattern, the second spacer structure including a third spacer and a fourth spacer.

12. The semiconductor device of claim 11 , further comprising a second impurity region at an upper portion of the substrate adjacent to a sidewall of the second spacer structure.

13. The semiconductor device of claim 11 , wherein the third gate structure includes a gate insulation layer, a first conductive pattern, a dielectric pattern, a second conductive pattern and a third conductive pattern sequentially stacked, and the first, second and third conductive patterns in the third gate structure are electrically connected to each other.

14. The semiconductor device of claim 11 , wherein an upper width of the second capping insulation pattern is less than a lower width of the second capping insulation pattern, and each of opposite sidewalls of the second capping insulation pattern has an inflection point.

15. A semiconductor device, comprising:
first gate structures on a first region of a substrate, each of the first gate structures having a first width;
second gate structures including sidewalls on the first region of the substrate, each of the second gate structures having a second width greater than the first width, wherein sidewalls of neighboring ones of the second gate structures oppose to each other;
a third gate structure on a second region of the substrate, the third gate structure having a third width greater than the second width;
first capping insulation patterns covering upper portions of the first and second gate structures, a first opening being between neighboring ones of the second gate structures;
a second capping insulation pattern on the third gate structure;
a first spacer structure on sidewalls of each of the second gate structures and each of the first capping insulation patterns exposed by the first opening, the first spacer structure including a first spacer and a second spacer; and
a second spacer structure on sidewalls of the third gate structure and the second capping insulation pattern, the second spacer structure including a third spacer and a fourth spacer.

16. The semiconductor device of claim 15 , wherein the first spacer includes a material different from a material of the second spacer, and the third spacer includes a material different from a material of the fourth spacer.

17. The semiconductor device of claim 15 , wherein the first spacer includes a material substantially the same as a material of the third spacer, and the second spacer includes a material different from a material of the fourth spacer.

18. The semiconductor device of claim 15 , wherein the first spacer includes a first curved portion between the second gate structure and an upper surface of the substrate, and the third spacer includes a second curved portion between the third gate structure and the upper surface of the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong-Won
• Park Bong-Tae
• Seong Ho-Jun
• Sim Jae-Hwang
• Jun Jung-Hoon

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title