Package-on-package semiconductor device

Patent metadata

Field	Value
Publication number	US-10083940-B2
Application number	US-201715622166-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Aug 24, 2012
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first die coupled beneath a lower surface of the substrate;
a second die coupled beneath the lower surface of the substrate and disposed over the first die;
a thermal contact pad arranged beneath a lower surface of the second die and an upper surface of the first die, wherein the thermal contact pad thermally isolates the first die from the second die; and
a molding compound separating the upper surface of the first die and/or an upper surface of the second die from the lower surface of the substrate.

2. The semiconductor device of claim 1 , wherein the thermal contact pad has outer sidewalls which are aligned with corresponding outer sidewalls of the second die.

3. The semiconductor device of claim 1 , wherein the first die has a first width as measured between outer sidewalls of the first die, and wherein the second die has a second width, which is less than the first width, as measured between outer sidewalls of the second die, and wherein the thermal contact pad has a third width as measured between outer sidewalls of the thermal contact pad, the third width being equal to the second width.

4. The semiconductor device of claim 1 , further comprising:
conductive elements extending through the substrate and coupled to the first die and the second die.

5. The semiconductor device of claim 1 ,
wherein the molding compound separates the upper surface of the first die from the lower surface of the substrate and separates the upper surface of the second die from the lower surface of the substrate.

6. The semiconductor device of claim 5 , further comprising:
conductive elements extending through the molding compound and through the substrate and coupled to the first die and the second die.

7. The semiconductor device of claim 6 , further comprising:
solder balls or solder bumps disposed over an upper surface of the substrate, the solder balls or solder bumps being electrically coupled to the conductive elements.

8. A semiconductor device comprising:
a first die having an upper surface and a lower surface;
a thermal contact pad arranged over a first portion of the upper surface of the first die and not covering a second portion of the upper surface of the first die;
a second die disposed over an upper surface of the thermal contact pad, wherein the second die is thermally isolated from the first die by the thermal contact pad; and
conductive elements being coupled to an upper surface of the second die and being coupled to the second portion of the upper surface of the first die.

9. The semiconductor device of claim 8 , further comprising:
a substrate over the upper surface of the first die.

10. The semiconductor device of claim 9 , further comprising:
a molding compound separating the upper surface of the first die from a lower surface of the substrate.

11. The semiconductor device of claim 10 , wherein the conductive elements extend through the molding compound and through the substrate to be coupled to the first die.

12. The semiconductor device of claim 11 , wherein the molding compound separates the upper surface of the second die from the lower surface of the substrate, and wherein the conductive elements extend through the molding compound and through the substrate to be coupled to the second die.

13. The semiconductor device of claim 11 , further comprising:
solder balls or solder bumps disposed over an upper surface of the substrate, the solder balls or solder bumps being electrically coupled to the conductive elements.

14. The semiconductor device of claim 8 , further comprising:
a seal ring arranged between the first die and the second die and circumscribing the thermal contact pad.

15. A semiconductor device comprising:
a first die having an upper surface and a lower surface;
a thermal contact pad arranged over a first portion of the upper surface of the first die and not covering a second portion of the upper surface of the first die;
a second die disposed over an upper surface of the thermal contact pad, wherein the second die is thermally isolated from the first die by the thermal contact pad; and
a molding compound over the upper surface of the first die and over an upper surface of the second die; and
conductive elements extending through the molding compound to be coupled to the first die and the second die.

16. The semiconductor device of claim 15 , wherein the conductive elements comprise one or more wire bonds which electrically couple the first die to the second die.

17. The semiconductor device of claim 15 , wherein the conductive elements comprise conductive pads, conductive pillars or conductive vias to electrically couple the first die to the second die.

18. The semiconductor device of claim 15 , further comprising:
a seal ring arranged between the first die and the second die and circumscribing the thermal contact pad.

19. The semiconductor device of claim 15 , further comprising:
a substrate over the upper surface of the second die, wherein the molding compound separates the upper surface of the second die from the lower surface of the substrate.

20. The semiconductor device of claim 19 , wherein the conductive elements extend through the molding compound and through the substrate to be coupled to the second die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yeh Der-Chyang

Classifications

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title