Transistor arrangement with semiconductor chips between two substrates

Patent metadata

Field	Value
Publication number	US-9806029-B2
Application number	US-201314044232-A
Country	US
Kind code	B2
Filing date	Oct 2, 2013
Priority date	Oct 2, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.

First claim

What is claimed is:

1. An electronic device, comprising:
a first substrate;
a second substrate;
a first semiconductor chip comprising a transistor, a first mounting surface bonded to the first substrate and a second mounting surface bonded to the second substrate;
a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate;
wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.

2. The device according to claim 1 , wherein the first semiconductor chip comprises a third transistor terminal at its first mounting surface.

3. The device according to claim 2 , wherein the first transistor terminal is a gate terminal, the second transistor terminal is a first source/drain terminal, and the third transistor terminal is a second source/drain terminal.

4. The device according to claim 1 , wherein the second semiconductor chip comprises a further transistor.

5. The device according to claim 4 , wherein the further transistor comprises a first transistor terminal and a second transistor terminal at its first mounting surface and a third transistor terminal at its second mounting surface.

6. The device according to claim 5 , wherein the first transistor terminal of the further transistor is a gate terminal, the second transistor terminal of the further transistor is a first source/drain terminal, and the third transistor terminal of the further transistor is a second source/drain terminal.

7. The device according to claim 1 , wherein the second semiconductor chip comprises a diode having a cathode and an anode.

8. The device according to claim 1 , wherein the electronic device is configured as a half bridge in which the transistor is configured as high-side switch and the second semiconductor chip comprises an assigned low side switch.

9. The device according to claim 1 , wherein the first substrate comprises a leadframe having a plurality of electrically conductive connection elements for electrically connecting the first mounting surface of the first semiconductor chip and the first mounting surface of the second semiconductor chip.

10. The device according to claim 1 , wherein the second substrate is a bonding clip, in particular a bonding clip connected in a cantilever fashion to the first substrate.

11. The device according to claim 10 , wherein the bonding clip is made of a thermally conductive and electrically conductive material.

12. The device according to claim 10 , wherein the bonding clip covers the entire second mounting surface of the first semiconductor chip and covers the entire second mounting surface of the second semiconductor chip.

13. The device according to claim 1 , comprising a driving unit mounted on the first substrate and configured for driving at least one of the first semiconductor chip and the second semiconductor chip.

14. The device according to claim 1 , configured as at least one of the group consisting of a half bridge, a cascaded power stage, a multi-half bridge, an H-bridge, and an electric engine controller.

15. An electronic power device, comprising:
a first substrate
a second substrate;
a first semiconductor power chip comprising a first transistor, a first mounting surface with two transistor terminals bonded to the first substrate and a second mounting surface with one transistor terminal bonded to the second substrate;
a second semiconductor power chip comprising a second transistor, a first mounting surface with two transistor terminals bonded to the first substrate and a second mounting surface with one transistor terminal bonded to the second substrate;
wherein, in a plan view perpendicular to the mounting surfaces, the second substrate covers the entire second mounting surface of the first semiconductor power chip and the entire second mounting surface of the second semiconductor power chip.

16. The device according to claim 15 , wherein the second substrate is a bonding clip.

17. The device according to claim 15 , wherein the first semiconductor power chip comprises a via extending through the first semiconductor power chip perpendicular to the mounting surfaces and electrically coupling one of the transistor terminals at its first mounting surface with the transistor terminal at its second mounting surface.

18. The device according to claim 17 , wherein the transistor terminal at the first mounting surface coupled by the via is a gate terminal, and wherein the transistor terminal at the second mounting surface coupled by the via is a source/drain terminal.

19. The device according to claim 15 , wherein the semiconductor power chips are connected to one another to form a half bridge.

20. A method of manufacturing an electronic device, wherein the method comprises:
bonding a first mounting surface of a first semiconductor chip to a first substrate;
bonding a first mounting surface of a second semiconductor chip to the first substrate;
bonding a second mounting surface of the first semiconductor chip to a second substrate;
bonding a second mounting surface of the second semiconductor chip to the second substrate;
forming a via extending through the first semiconductor chip for electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Otremba Ralf
• Hoeglauer Josef
• Chong Chooi Mei

Classifications

• H10W72/07653

  changes in shapes · CPC title

• H10W72/631

  Shapes of strap connectors · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title