Memory controller, memory module and memory system

Patent metadata

Field	Value
Publication number	US-10083728-B2
Application number	US-201414324228-A
Country	US
Kind code	B2
Filing date	Jul 6, 2014
Priority date	Sep 6, 2013
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

First claim

What is claimed is:

1. A memory controller, comprising:
a chip-select transmitter, arranged to generate a plurality of signals that operate differentially to select a first memory device from a plurality of memory devices, the plurality of signals comprising a first signal and a second signal which is an inversed version of the first signal;
a first terminal, arranged to output the first signal; and
a second terminal, arranged to output the second signal;
wherein the first signal and the second signal are a pair of differential signals;
wherein the second terminal is configured to send the second signal such that the second signal bypasses the plurality of memory devices;
wherein the chip-select transmitter generates the first signal and the second signal synchronously.

2. The memory controller of claim 1 , wherein when a notification is acquired to be performed by the first signal and the second signal, the first signal is asserted to a first voltage level for a specific time interval, and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.

3. The memory controller of claim 2 , wherein the memory controller further provides a clock output, and the specific time interval equals to a period of the clock output.

4. The memory controller of claim 1 , wherein the memory controller is a DDR3 memory controller for controlling a DDR3 memory module.

5. A memory module, comprising:
a first terminal, arranged to receive a first signal for enabling a first memory chip of a plurality of memory chips;
a second terminal, arranged to receive a second signal for enabling the first memory chip of the plurality of memory chips;
a first conducting path, having a first end coupled to the first terminal;
the plurality of memory chips, coupled to the first conducting path for receiving the first signal;
a resistor, having a first terminal coupled to a second end of the first conducting path; and
a second conducting path, having a first end coupled to the second terminal for conducting the second signal to a second terminal of the resistor such that the second conducting path bypasses the plurality of memory chips;
wherein the first signal and the second signal are synchronous and a pair of differential signals that operate differentially to enable the first memory chip to be accessed,
wherein the second signal is an inversed version of the first signal.

6. The memory module of claim 5 , wherein the first signal and the second signal reach the resistor substantially at the same time via the first conducting path and the second conducting path, respectively.

7. The memory module of claim 5 , wherein a first impedance obtained by looking into the second end of the first conducting path substantially equals a second impedance obtained by looking into the first terminal of the resistor.

8. The memory module of claim 5 , wherein the first signal is asserted to a first voltage level for a specific time interval, and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.

9. The memory module of claim 8 , wherein the memory controller further receives a clock input, and the specific time interval equals to a period of the clock output.

10. The memory module of claim 5 , wherein the memory module is a DDR3 memory module.

11. The memory module of claim 5 , wherein the resistor is a 100 Ohm resistor.

12. A memory system, comprising:
a memory controller; and
a memory module comprising a plurality of memory chips;
wherein the memory controller generates a differential pair of a first signal and a second signal, and the first signal and the second signal are synchronous with each other and operate differentially on a selected memory chip of the plurality of memory chips to enable the selected memory chip to be accessed by the memory controller;
wherein the second signal bypasses the plurality of memory chips; and
wherein the second signal is an inversed version of the first signal.

13. The memory system of claim 12 , wherein when a notification is acquired to be performed by the first signal and the second signal, the first signal is asserted to a first voltage level for a specific time interval, and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.

14. The memory system of claim 13 , wherein the memory controller further provides a clock output to the memory module, and the specific time interval equals to a period of the clock output.

15. The memory system of claim 12 , wherein the memory module receives the first signal and the second signal by a first terminal and a second terminal respectively; and a first impedance obtained by looking into the second terminal substantially equals a second impedance obtained by looking into the first terminal.

16. The memory module of claim 15 , wherein each of the first and second impedance is equal to 50 Ohm.

17. The memory system of claim 12 , wherein the memory controller is a DDR3 memory controller, and the memory module is a DDR3 memory module.

18. The memory system of claim 12 , wherein the memory module comprises first and second resistors.

19. The memory module of claim 18 , wherein each of the first and second resistors is a 100 Ohm resistor.

Assignees

• Mediatek Inc

Inventors

• Luo Yan-Bin
• Chang Sheng-Ming
• Hsieh Bo-Wei
• Liou Ming-Shi
• Hung Chih-Chien
• Chen Shang-Pin

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C8/12 Primary

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title