Method and apparatus for configuring write performance for electrically writable memory devices

Patent metadata

Field	Value
Publication number	US-10082976-B2
Application number	US-201514921877-A
Country	US
Kind code	B2
Filing date	Oct 23, 2015
Priority date	Dec 17, 2008
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.

First claim

What is claimed is:

1. A nonvolatile memory comprising:
one or more memory cells configured to store information; and
a configuration register configured to determine an entire amount of available current for the nonvolatile memory based at least in part on a number of idle components within the nonvolatile memory, and dynamically adjust a write speed for a write operation to the one or more memory cells based at least in part on the determined entire amount of available current for the nonvolatile memory, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

2. The nonvolatile memory of claim 1 , further comprising one or more program bandwidth switches configured to indicate a number of bits that may be simultaneously programmed in the one or more memory cells.

3. The nonvolatile memory of claim 2 , wherein the write speed of the write operations is increased by increasing the number of bits that are simultaneously programmed in the one or more memory cells.

4. The nonvolatile memory of claim 1 , wherein the write speed of the write operations is increased by increasing the current supplied for the write operations based at least in part on a setting of the configuration register.

5. The nonvolatile memory of claim 1 , wherein a performance speed of the write operation is based at least in part on an amount of current supplied to the nonvolatile memory.

6. The nonvolatile memory of claim 1 , wherein the configuration register includes a reference table configured to indicate the write speed based at least in part on a setting of the configuration register.

7. The nonvolatile memory of claim 1 , wherein the write speed is fixed to maintain a fixed speed of the write operation.

8. The nonvolatile memory of claim 1 , wherein the information comprises at least one of data or program code.

9. The nonvolatile memory of claim 1 , wherein the nonvolatile memory comprises at least one of a Phase-Change Memory (“PCM”), flash memory, and/or Electrically Erasable Programmable Read-Only Memory (“EEPROM”).

10. The nonvolatile memory of claim 1 , wherein the write speed is user-selectable.

11. The nonvolatile memory of claim 1 , wherein the configuration register is configured to identify an amount of available current for the nonvolatile memory.

12. A nonvolatile memory comprising:
one or more memory cells configured to store information;
a configuration register configured to indicate a write speed for a write operation to the one or more memory cells, the write speed based at least in part on an amount of available current for the nonvolatile memory; and
a global program state machine configured by values stored in the configuration register, the global program state machine configured to contain data to be programmed to the one or more memory cells, the data associated with the information stored in the one or more memory cells, wherein the write speed is dynamic, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

13. A nonvolatile memory comprising:
one or more memory cells configured to store information;
a configuration register configured to indicate a write speed for a write operation to the one or more memory cells, the write speed based at least in part on an amount of available current for the nonvolatile memory; and
one or more program state machines configured to program the one or more memory cells by pulsing the one or more memory cells with the current supplied for the write operations, wherein the global program state machine is configured to write data to be programmed to the one or more program state machines, and
wherein the write speed is dynamic, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

14. A method, comprising:
determining a write speed for write operations to a nonvolatile memory based at least in part on an entire amount of available current that is based at least in part on a number of idle components within the nonvolatile memory;
supplying an amount of current to perform a write operation to the nonvolatile memory at the write speed, wherein the amount of current supplied is less than or equal to the entire amount of available current; and
dynamically adjusting the write speed based at least in part on the entire amount of available current, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

15. The method of claim 14 , further comprising changing the write speed of the write operations to the nonvolatile memory by changing the amount of current supplied for the write operations, the write speed of the write operations to the nonvolatile memory based at least in part on the amount of current supplied for the write operations.

16. The method of claim 15 , wherein changing the write speed comprises increasing the write speed by increasing the amount of current supplied for the write operations.

17. The method of claim 14 , further comprising supplying an amount of current to perform a write operation to the nonvolatile memory at a fixed speed.

18. The method of claim 14 , further comprising selecting the write speed.

19. A nonvolatile memory comprising:
at least one memory cell configured to store information,
wherein a write operation stores the information in the at least one memory cell at a write speed that is dynamically adjusted based at least in part on an entire amount of available current for the nonvolatile memory that is based at least in part on a number of idle components within the nonvolatile memory, and
wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

20. The nonvolatile memory of claim 19 , wherein the write speed of the write operations is changed by controlling the current supplied for the write operations.

21. The nonvolatile memory of claim 20 , wherein the write speed of the write operations is increased by increasing the current supplied for the write operations based at least in part on the amount of available current.

Assignees

• Micron Technology Inc

Inventors

• Barkley Gerald
• Kale Poorna

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title