Switched-capacitor bandgap reference circuit using chopping technique

Patent metadata

Field	Value
Publication number	US-10082819-B2
Application number	US-201615335367-A
Country	US
Kind code	B2
Filing date	Oct 26, 2016
Priority date	Oct 26, 2015
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.

First claim

What is claimed is:

1. A method comprising:
providing, during a first time interval, a first voltage to a first output node, wherein the first voltage is provided as an output signal of a chopped operational amplifier (op-amp), and wherein the first voltage includes (i) a proportional-to-absolute-temperature (PTAT) component, (ii) a complementary-to-absolute-temperature (CTAT) component, and (iii) a first residual offset component;
providing, during a second time interval, a second voltage to the first output node, wherein the second voltage is also provided as the output signal of the chopped op-amp, and wherein the second voltage includes (i) the PTAT component, (ii) the CTAT component, and (iii) a second residual offset component; and
averaging the first voltage and the second voltage to provide a reference voltage to a second output node.

2. The method of claim 1 , further comprising:
coupling a first end of a first capacitive element to the first output node according to a first switching signal; and
coupling a first end of a second capacitive element to the first output node according to a second switching signal,
wherein a second end of the first capacitive element and a second end of the second capacitive element are coupled to a ground.

3. The method of claim 2 , further comprising:
coupling a first end of a third capacitive element to the first end of the first capacitive element and the first end of the second capacitive element according to a third switching signal,
wherein the first end of the third capacitive element is coupled to the second output node and a second end of the third capacitive element is coupled to the ground.

4. The method of claim 1 , further comprising:
coupling a first input node to a first signal path of the chopped op-amp according to a clock signal indicative of a first value and a phase signal indicative of a first phase;
coupling the first output node to a second signal path of the chopped op-amp according to the clock signal indicative of the first value and the phase signal indicative of the first phase;
coupling first ends of first, second, and third capacitive elements to the second signal path of the chopped op-amp according to the phase signal indicative of the first phase; and
coupling a second end of the third capacitive element to a ground according to the clock signal indicative of the first value.

5. The method of claim 4 , further comprising:
coupling a second input node to the first signal path of the chopped op-amp according to the clock signal indicative of a second value and the phase signal indicative of the first phase;
decoupling the second end of the third capacitive element from the ground according to the clock signal indicative of the second value;
coupling a second end of the second capacitive element to the second end of the third capacitive element according to the clock signal indicative of the second value; and
adjusting a level of a voltage at the first output node to provide the first voltage.

6. The method of claim 4 , further comprising:
coupling the first input node to a third signal path of the chopped op-amp according to the clock signal indicative of the first value and the phase signal indicative of a second phase; and
coupling the first ends of the first, second, and third capacitive elements to a fourth signal path of the chopped op-amp according to the phase signal indicative of the second phase.

7. The method of claim 6 , further comprising:
coupling a second input node to the third signal path of the chopped op-amp according to the clock signal indicative of a second value and the phase signal indicative of the second phase;
decoupling the second end of the third capacitive element from the ground according to the clock signal indicative of the second value;
coupling a second end of the second capacitive element to the second end of the third capacitive element according to the clock signal indicative of the second value; and
adjusting a level of a voltage at the first output node to provide the second voltage.

8. The method of claim 1 , wherein the chopped op-amp is a first chopped op-amp, the method further comprising:
generating a PTAT current using a second chopped op-amp according to a phase signal; and
multiplying the PTAT component, the CTAT component, and the first residual offset component and adding the multiplied PTAT component, CTAT component, and first residual offset component to provide the first voltage using the first chopped op-amp according to the phase signal indicative of a first phase and a clock signal.

9. The method of claim 8 , further comprising:
multiplying the PTAT component, the CTAT component, and the second residual offset component and adding the multiplied PTAT component, CTAT component, and second residual offset component to provide the second voltage using the first chopped op-amp according to the phase signal indicative of a second phase and the clock signal,
wherein each of the first and second residual offset components is associated with a first offset of the first chopped op-amp and a second offset of the second chopped op-amp.

10. An apparatus comprising:
a discrete-time circuit to provide a first voltage to a first output node during a first time interval and to provide a second voltage to the first output node during a second time interval, the first voltage including a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component, the second voltage including the PTAT component, the CTAT component, and a second residual offset component; and
a filter to average the first and second voltages to provide a reference voltage to a second output node,
wherein the discrete-time circuit includes a chopped operational amplifier (op-amp), and wherein the chopped op-amp (i) provides, during the first time interval, the first voltage as an output signal to the first output node, and (ii) provides, during the second time interval, the second voltage as the output signal to the first output node.

11. The apparatus of claim 10 , wherein the filter includes:
a first capacitive element coupled to the first output node and a ground;
a first switching device to couple a first end of the first capacitive element to the first output node according to a first switching signal;
a second capacitive element coupled to the first output node and the ground; and
a second switching device to couple a first end of the second capacitive element to the first output node according to a second switching signal,
wherein a second end of the first capacitive element and a second end of the second capacitive element are coupled to the ground.

12. The apparatus of claim 11 , wherein the filter further includes:
a third capacitive element coupled to the second output node and the ground;
a third switching device to couple a first end of the third capacitive element and a third output node according to a third switching signal;
a fourth switching device to couple the first end of the first capacitive element to the third output node according to a fourth switching signal; and
a fifth switching device to couple the first end of the second capacitive element to the third output node according to a fifth switching signal.

13. The apparatus of claim 10 , wherein the discrete-time circuit is a switched capacitor circuit,
wherein the chopped op-amp includes a first switching network, an op-amp, a second switching network, and an output, the first and second switching networks to provide first and second signal paths according to a phas

Assignees

• Marvell World Trade Ltd

Inventors

• Xu Weiwei
• Upadhyaya Prasanna
• Liu Norman
• Wang Xiaoyue

Classifications

• H03F3/393

  with field-effect devices · CPC title

• H03F2200/271

  the DC-isolation amplifier, e.g. chopper amplifier, modulation/demodulation amplifier, uses capacitive isolation means, e.g. capacitors · CPC title

• H03F3/45968

  by offset reduction · CPC title

• G05F3/30 Primary

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

• H03F2203/45286

  the temperature dependence of a differential amplifier being controlled · CPC title