Built-in self-test for ADC

Patent metadata

Field	Value
Publication number	US-10079610-B2
Application number	US-201615742435-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Jul 7, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.

First claim

The invention claimed is:

1. A built-in self-test, BIST arrangement for an analog-to-digital converter, ADC, comprising:
a charging circuit arranged to charge at least one capacitance of a capacitor array of the ADC;
a discharging circuit arranged to discharge the at least one capacitance; and
a logic portion arranged to evaluate results of the charging circuit and the discharging circuit and to determine whether the ADC is functioning within specified parameters based on the results, at least a portion of the charging circuit and/or the discharging circuit comprising one or more components of the ADC,
wherein the charging circuit and/or the discharging circuit comprise a switched capacitor discharger circuit arranged to measure a capacitance of the at least one capacitance of the ADC, wherein the switched capacitor discharger circuit comprises an additional capacitor separate from the capacitor array of the ADC, further comprising a comparator and a clock counter, the counter being gated by the comparator, wherein a first input of the comparator is coupled to a node between the capacitor array and the additional capacitor, and a second input of the comparator is to be coupled to a comparator threshold voltage.

2. The BIST of claim 1 , wherein the counter stores a value that represents a timing between comparator threshold voltage crossings.

3. The BIST of claim 2 , wherein an equal timing between comparator crossings is an indication of a desired capacitor match within a capacitor array of the ADC.

4. The BIST of claim 1 , wherein the BIST arrangement is integral to the ADC and is fully contained on an integrated circuit (IC) chip of the ADC.

5. The BIST of claim 1 , wherein the charging circuit and/or the discharging circuit use one or more of a switch, a capacitance, or a comparator of the ADC to generate a test stimulus and to evaluate a result of applying the test stimulus to the ADC for testing the ADC.

6. The BIST of claim 1 , wherein the logic portion is arranged to control the charging and the discharging of the at least one capacitance and to determine a value for the at least one capacitance.

7. The BIST of claim 1 , wherein the BIST is arranged to test a functionality of a capacitor array of the ADC, a comparator of the ADC, a switch of the ADC, and/or a buffer of the ADC.

8. The BIST of claim 1 ,
wherein the logic portion is configured to determine a differential nonlinearity or an integral nonlinearity of the ADC based on the results.

9. The BIST of claim 1 ,
wherein the BIST is adapted to perform the charging for all capacitances of the capacitor array to obtain a nonlinear equation system, and to solve the equation system to obtain capacitance values.

10. An analog-to-digital converter (ADC), comprising:
a successive approximation register (SAR) arranged to convert an analog input to a digital approximation;
a digital-to-analog converter (DAC) capacitance comprising a non-binary-weighted capacitor array of multiple switched capacitances and arranged to convert the digital approximation to an analog form;
a comparator arranged to compare an analog output of the DAC with the analog input; and
a built-in self-test (BIST) arranged to test one or more components of the ADC to determine whether the one or more components are functioning within specified parameters, the BIST also comprising one or more of the multiple switched capacitances and/or the comparator, wherein the BIST comprises:
a charging circuit arranged to charge at least one capacitance of the capacitor array;
a discharging circuit arranged to discharge the at least one capacitance; and
a logic portion arranged to evaluate results of the charging circuit and the discharging circuit and to determine whether the ADC is functioning within specified parameters based on the results, at least a portion of the charging circuit and/or the discharging circuit comprising one or more components of the ADC,
wherein the charging circuit and/or the discharging circuit comprise a switched capacitor discharger circuit arranged to measure a capacitance of the at least one capacitance of the ADC, wherein the switched capacitor discharger circuit comprises an additional capacitor separate from the capacitor array of the ADC, further comprising a comparator and a clock counter, the counter being gated by the comparator, wherein a first input of the comparator is coupled to a node between the capacitor array and the additional capacitor, and a second input of the comparator is to be coupled to a comparator threshold voltage.

11. The ADC of claim 10 , further comprising a quantity of switches coupled to the multiple switched capacitances and arranged as a multiplexer to couple each of the multiple switched capacitances to a reference voltage or to ground, or to float during testing of the one or more components of the ADC.

12. The ADC of claim 10 the charging circuit and a discharging circuit being arranged to generate a test stimulus signal and an evaluation circuit arranged to evaluate a result of applying the test stimulus signal to the ADC, wherein the charging circuit, discharging circuit, and evaluation circuit are located on a same chip as the ADC.

13. The ADC of claim 12 , wherein the BIST further comprises a comparator set with a dynamic threshold based on a ratio of a single capacitance value of an array of multiple capacitances of the ADC to a total active capacitance value of the array.

14. The ADC of claim 13 , wherein the active capacitance value comprises a total capacitance value of the array less a capacitance of one or more of the multiple capacitances that are set to float.

15. The ADC of claim 13 wherein the BIST is arranged to characterize the array of multiple capacitances by measuring thresholds of capacitances representing each bit position of the array successively, the characterizing including determining a capacitance match of the array.

16. The ADC of claim 10 , wherein the BIST is fully contained on an integrated circuit (IC) chip of the ADC.

17. A method, comprising:
charging and discharging at least one capacitance of a capacitor array of an analog-to-digital converter (ADC) using a charging circuit and/or a discharging circuit, wherein the charging circuit and/or the discharging circuit comprise a switched capacitor discharger circuit arranged to measure a capacitance of the at least one capacitance of the ADC, wherein the switched capacitor discharger circuit comprises an additional capacitor separate from the capacitor array of the ADC, further comprising a comparator and a clock counter, the counter being gated by the comparator, wherein a first input of the comparator is coupled to a node between the capacitor array and the additional capacitor, and a second input of the comparator is to be coupled to a comparator threshold voltage;
comparing a charged or discharged voltage of the at least one capacitance to a threshold; and
determining a capacitance value of the at least one capacitance based on a passage of time before the threshold is crossed by the charged or discharged voltage, the charging, discharging, comparing, and determining performed using components co-located with the ADC on a single chip.

18. The method of claim 17 , further comprising updating a voltage of the threshold when the charged or discharged voltage crosses the threshold.

19. The method of claim 18 , further comprising determining the capacitance value of the at least one capacitance based on a quantity of iterations of charging, discharging, and comparing until t

Assignees

• Infineon Technologies Ag

Inventors

• Bogner Peter
• Kalt Andreas
• Mejri Jaafar
• Pernull Martin

Classifications

• H03M1/804

  with charge redistribution · CPC title

• H03M1/109 Primary

  for DC performance, i.e. static testing (H03M1/1085 takes precedence) · CPC title

• H03M1/1071 Primary

  Measuring or testing · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title