Wideband adaptive bias circuits for power amplifiers

Patent metadata

Field	Value
Publication number	US-10079574-B2
Application number	US-201615019409-A
Country	US
Kind code	B2
Filing date	Feb 9, 2016
Priority date	Feb 9, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

First claim

What is claimed is:

1. An adaptive bias circuit, comprising:
a first detector circuit configured to output a first current based on an input power, wherein the first detector circuit is configured to clamp the first current at a first input power level; and
a second detector circuit configured to output a second current based on the input power, wherein the second detector circuit is configured to clamp the second current at a second input power level lower than the first input power level;
wherein the first detector circuit and the second detector circuit are arranged to provide an output current that subtracts the second current from the first current.

2. The adaptive bias circuit of claim 1 , wherein the first detector circuit comprises a first pair of coupling capacitors configured to set the first input power level at which the first current is clamped, and wherein the second detector circuit comprises a second pair of coupling capacitors configured to set the second input power level at which the second current is clamped.

3. The adaptive bias circuit of claim 1 , further comprising:
a first current mirror circuit configured to mirror the second current to a first node in the adaptive bias circuit that performs the subtraction of the second current from the first current.

4. The adaptive bias circuit of claim 3 , further comprising:
a constant current source, wherein the constant current source is arranged to adjust a response characteristic of the output current.

5. The adaptive bias circuit of claim 4 , further comprising:
a second current mirror circuit configured to mirror the output current to a second node in the adaptive bias circuit that performs the adjustment of the response characteristic of the output current.

6. The adaptive bias circuit of claim 1 , wherein the first detector circuit and the second detector circuit each includes a plurality of MOSFETs configured to remain active across multiple input power levels to provide wideband adaptive biasing.

7. The adaptive bias circuit of claim 1 , wherein the first current output from the first detector circuit and/or the second current output from second detector circuit results from algorithmic operations of the outputs from multiple detectors.

8. The adaptive bias circuit of claim 1 , further comprising:
a current mirror circuit configured to mirror the first current output from the first detector circuit to a node in the adaptive bias circuit that performs the subtraction of the second current from the first current; and
a constant current source coupled to the node.

9. The adaptive bias circuit of claim 8 , wherein the first detector circuit comprises a first pair of coupling capacitors configured to set the first input power level at which the first current is clamped, and wherein the second detector circuit comprises a second pair of coupling capacitors configured to set the second input power level at which the second current is clamped.

10. An adaptive bias circuit, comprising:
a first detector circuit configured to output a first current based on an input power, wherein the first detector circuit is configured to clamp the first current at a first input power level;
a second detector circuit configured to output a second current based on the input power, wherein the second detector circuit is configured to clamp the second current at a second input power level lower than the first input power level, wherein the first detector circuit and the second detector circuit are arranged to provide an output current that subtracts the second current from the first current at a node of the adaptive bias circuit; and
a tuning circuit configured to tune a transfer function of the output current.

11. The adaptive bias circuit of claim 10 , wherein the tuning circuit comprises:
a pair of cascode transistors include a first transistor and a second transistor, wherein the first transistor is configured to MOSFET coupled to the node, wherein the first transistor and second transistor are configured to have different operating conditions.

12. The adaptive bias circuit of claim 10 , wherein the tuning circuit comprises a plurality of detector cells, wherein at least some of the plurality of detector cells are configured to be selectively turned on or off to tune the transfer function.

Assignees

• Mediatek Inc

Inventors

• Yu Hsing-ting
• Song Fei
• Wu I-Chang
• Chee Yuenhui
• Lu Chiyuan
• Fong Keng Leong
• Shana'A Osama K A

Classifications

• H03F1/0222 Primary

  by using a signal derived from the input signal · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title

• H03F2203/21106

  An input signal being distributed in parallel over the inputs of a plurality of power amplifiers · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title