Methods and apparatuses for slew rate enhancement of amplifiers

Patent metadata

Field	Value
Publication number	US-9431968-B2
Application number	US-201414212741-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 15, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition.

First claim

What is claimed is:

1. A circuit to enhance slew rate, comprising:
an amplifier comprising a positive input operably coupled to a first side of an amplifier differential pair, a negative input operably coupled to a second side of the amplifier differential pair, and an output;
a first slew direction enhancer comprising a first differential pair, wherein the first differential pair has a first transistor and a second transistor, is operably coupled to the positive input and the negative input is configured to cause the first slew direction enhancer to provide additional current for the first side of the amplifier differential pair during an offset in a first direction between the positive input and the negative input, and wherein a gate length of the first transistor is shorter than a gate length of the second transistor to detect the offset in the first direction after the amplifier differential pair detects the offset in the first direction; and
a second slew direction enhancer comprising a second differential pair operably coupled to the positive input and the negative input, wherein the second differential pair is configured to cause the second slew direction enhancer to provide additional current for the second side of the amplifier differential pair during an offset in a second direction between the positive input and the negative input.

2. The circuit of claim 1 , wherein the second differential pair includes transistor sizes skewed to detect the offset in the second direction after the amplifier differential pair detects the offset in the second direction.

3. The circuit of claim 2 , wherein a gate length of a first transistor of the second differential pair is shorter than a gate length of a second transistor of the second differential pair to create a skew in the transistor sizes.

4. The circuit of claim 1 , wherein the first slew direction enhancer further comprises:
a first control node operably coupled to one transistor of the first differential pair and configured to go to a low voltage during the offset in the first direction; and
a first pull-up transistor configured to provide the additional current for the first side of the amplifier differential pair responsive to the low voltage on the first control node.

5. The circuit of claim 4 , wherein the first slew direction enhancer further comprises a second pull-up transistor configured to pull the first control node to a high voltage when the offset in the first direction is not present such that the first pull-up transistor will be shut off.

6. The circuit of claim 1 , wherein the second slew direction enhancer further comprises:
a first control node operably coupled to one transistor of the second differential pair and configured to go to a low voltage during the offset in the second direction; and
a first pull-up transistor configured to provide the additional current for the second side of the amplifier differential pair responsive to the low voltage on the first control node.

7. The circuit of claim 6 , wherein the second slew direction enhancer further comprises a second pull-up transistor configured to pull the first control node to a high voltage when the offset in the second direction is not present such that the first pull-up transistor will be shut off.

8. A circuit to enhance slew rate, comprising:
an amplifier comprising a first input and a second input in a differential pair configuration and an output, the differential pair configuration having a first side and a second side;
a slew rate enhancer comprising:
a first slew direction enhancer configured to:
detect a first slew rate condition in a first direction responsive to the first input and the second input; and
provide additional current for the first side of the differential pair configuration of the amplifier during the first slew rate condition using a first pull-up transistor, the first pull-up transistor configured to supply an adjustment signal in response to a low voltage;

a second slew direction enhancer configured to:
detect a second slew rate condition in a second direction responsive to the first input and the second input; and
provide additional current for a second side of the differential pair configuration of the amplifier during the second slew rate condition.

9. The circuit of claim 8 , wherein the first slew direction enhancer is further configured to provide the additional current for the first side of the differential pair configuration of the amplifier after the first slew rate condition commences.

10. The circuit of claim 9 , wherein the first slew direction enhancer is further configured to detect a steady-state condition between the first input and the second input and prevent the additional current for the first side of the differential pair configuration of the amplifier during the steady-state condition.

11. The circuit of claim 8 , wherein the second slew direction enhancer is further configured to provide the additional current for the second side of the differential pair configuration of the amplifier after the second slew rate condition commences.

12. The circuit of claim 11 , wherein the second slew direction enhancer is further configured to detect a steady-state condition between the first input and the second input and prevent the additional current for the second side of the differential pair configuration of the amplifier during the steady-state condition.

13. The circuit of claim 8 , wherein the first slew direction enhancer further comprises:
a first control node operably coupled to a first transistor of the first slew direction enhancer and configured to go to a low voltage during the first slew rate condition; and
further wherein the second slew direction enhancer further comprises:
a second control node operably coupled to a first transistor of the second slew direction enhancer and configured to go to a low voltage during the second slew rate condition; and
a second pull-up transistor configured to provide the additional current for the second side of the differential pair configuration of the amplifier responsive to the low voltage on the second control node.

14. The circuit of claim 8 , wherein the first slew direction enhancer includes a first transistor and a second transistor wherein a gate length of the first transistor is shorter than a gate length of the second transistor.

15. A method of enhancing slew rate, comprising:
detecting a first slew rate condition responsive to a first offset in a first direction between a first input and a second input using a first differential pair;
providing additional current for a first side of a differential pair of an amplifier coupled to the first input and the second input during the first slew rate condition using a first pull-up transistor, the first pull-up transistor configured to supply an adjustment signal in response to a low voltage;
detecting a second slew rate condition responsive to a second offset in a second direction between the first input and the second input using a second differential pair; and
providing additional current for a second side of the differential pair of the amplifier during the second slew rate condition.

16. The method of claim 15 , wherein detecting the first slew rate condition further comprises detecting the first slew rate condition after the differential pair of the amplifier detects the first slew rate condition.

17. The method of claim 16 , further comprising detecting a steady-state condition between the first input and the second input and preventing the additional current for the first side o

Assignees

• Integrated Device Tech

Inventors

• Montazer G Hossein

Classifications

• H03F1/0261 Primary

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• H03F3/45192

  Folded cascode stages · CPC title

• H03F2203/45248

  the dif amp being designed for improving the slew rate · CPC title