Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10079298-B2
Application number	US-201615201211-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 23, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A semiconductor device includes on an n-type semiconductor substrate of silicon carbide, an n-type semiconductor layer, a p-type base region, an n-type source region, a p-type contact region, a gate insulating film, a gate electrode, and a source electrode. The semiconductor device has a drain electrode on a back surface of the semiconductor substrate. On a surface of the gate electrode, an interlayer insulating film is disposed. The interlayer insulating film has plural layers among which, one layer is formed by a silicon nitride film. With such a structure, degradation of semiconductor device properties are suppressed. Further, increases in the number of processes at the time of manufacturing are suppressed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type formed of silicon carbide;
a semiconductor layer of the first conductivity type, disposed on a first principal surface of the semiconductor substrate, and having an impurity concentration that is lower than that of the semiconductor substrate;
a base region of a second conductivity type, disposed on a surface of the semiconductor layer;
a source region of the first conductivity type, disposed in a first surface region of the base region;
a contact region of the second conductivity type, disposed in a second surface region of the base region, and having an impurity concentration that is higher than that of the base region;
a source electrode contacting the source region and the contact region;
a gate insulating film disposed on a surface of the base region, the base region being disposed between the semiconductor layer and the source region;
a gate electrode disposed on a surface of the gate insulating film;
an interlayer insulating film extending between a surface of the gate electrode and the source electrode, and including a plurality of layers, the plurality of layers including silicon oxide layers sandwiching a silicon nitride layer so as to prevent an impurity from diffusing into the semiconductor device, the silicon oxide layer disposed on an upper surface of the silicon nitride layer comprising a silicon oxide glass containing boron and phosphorus; and
a drain electrode disposed on a second principal surface of the semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein the silicon nitride layer has a thickness equal to or greater than 0.2 μm.

3. The semiconductor device according to claim 1 , wherein the first principal surface of the semiconductor substrate is in a plane parallel to or tilted within 10 degrees of a plane whose a crystallographic plane index is (000-1).

4. The semiconductor device according to claim 1 , wherein the first principal surface of the semiconductor substrate is in a plane parallel to or tilted within 10 degrees of a plane whose crystallographic plane index is (0001).

5. The semiconductor device according to claim 1 , wherein the silicon nitride layer has a thickness equal to or greater than 0.5 μm.

6. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type formed of silicon carbide;
a semiconductor layer of the first conductivity type, disposed on a first principal surface of the semiconductor substrate, and having an impurity concentration that is lower than that of the semiconductor substrate;
a semiconductor region of a second conductivity type, disposed in a portion of a surface region of the semiconductor layer;
a base region disposed on a surface of the semiconductor region and having an impurity concentration that is lower than that of the semiconductor region;
a well region of the first conductivity type formed of a silicon carbide, disposed on the surface of the semiconductor layer, contacting the base region, and having an impurity concentration that is lower than that of the semiconductor substrate;
a source region of the first conductivity type, disposed in a surface region of the base region and away from the well region, and having an impurity concentration that is higher than that of the well region;
a contact region of the second conductivity type, disposed in a surface of the base region and contacting the source region, and having an impurity concentration that is higher than that of the base region;
a source electrode contacting the source region and the contact region;
a gate insulating film disposed on a surface of the base region, the base region being disposed between the well region and the source region;
a gate electrode disposed on a surface of the gate insulating film;
an interlayer insulating film extending between a surface of the gate electrode and a source electrode, and including a plurality of layers, the plurality of layers including silicon oxide layers sandwiching a silicon nitride layer so as to prevent an impurity from diffusing into the semiconductor device, the silicon oxide layer disposed on an upper surface of the silicon nitride layer comprising a silicon oxide glass containing boron and phosphorus; and
a drain electrode disposed on a second principal surface of the semiconductor substrate.

7. The semiconductor device according to claim 6 , wherein the silicon nitride layer has a thickness equal to or greater than 0.2 μm.

8. The semiconductor device according to claim 6 , wherein the first principal surface of the semiconductor substrate is in a plane parallel to or tilted within 10 degrees of a plane whose crystallographic plane index is (000-1).

9. The semiconductor device according to claim 6 , wherein the first principal surface of the semiconductor substrate is in a plane parallel to or tilted within 10 degrees of a plane whose crystallographic plane index is (0001).

10. The semiconductor device according to claim 6 , wherein the silicon nitride layer has a thickness equal to or greater than 0.5 μm.

11. A method of manufacturing a semiconductor device, the method comprising
forming of silicon carbide a semiconductor substrate a first conductivity type;
forming a semiconductor layer of the first conductivity type on a first principal surface of the semiconductor substrate, to have an impurity concentration lower than that of the semiconductor substrate;
forming a base region of a second conductivity type on a surface of the semiconductor layer;
forming a source region of the first conductivity type in a first surface region of the base region;
forming a contact region of the second conductivity type on a second surface region of the base region, to have an impurity concentration greater than that of the base region;
forming a gate insulating film on a surface of the base region, the base region being formed between the semiconductor layer and the source region;
forming a gate electrode on a surface of the gate insulating film;
forming an interlayer insulating film on a surface of the gate electrode, including
forming the interlayer insulating film to include a plurality of layers, at least one of the plurality of layers being a silicon nitride layer, the plurality of layers including silicon oxide layers sandwiching the silicon nitride layer so as to prevent an impurity from diffusing into the semiconductor device, the silicon oxide layer formed on an upper surface of the silicon nitride layer comprising a silicon oxide glass containing boron and phosphorus;

forming a source electrode on the gate electrode, contacting the source region and the contact region; and
forming a drain electrode on a second principal surface of the semiconductor substrate.

12. A method of manufacturing a semiconductor device, the method comprising
forming of silicon carbide a semiconductor substrate of a first conductivity type;
forming a semiconductor layer of the first conductivity type on a first principal surface of the semiconductor substrate, to have an impurity concentration lower than that of the semiconductor substrate;
forming a semiconductor region of a second conductivity type in a portion of a surface region of the semiconductor layer;
forming a base region on a surface of the semiconductor region, to have an impurity concentration lower than that of the semiconductor region;
forming of a silicon carbide a well region of the first conductivity type, on the surface of the semiconductor layer and contacting the base region, to have an impurity concentration lower than that of the semiconductor

Assignees

• Fuji Electric Co Ltd

Inventors

• Kinoshita Akimasa
• Hoshi Yasuyuki
• Harada Yuichi
• Sakai Yoshiyuki
• Iwaya Masanobu
• Ryo Mina

Classifications

• H01L29/41741

  Electricity · mapped topic

• H01L29/0878

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic