Integrated circuit device and method of fabricating the same

US10079210B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10079210-B2
Application numberUS-201615186825-A
CountryUS
Kind codeB2
Filing dateJun 20, 2016
Priority dateOct 12, 2015
Publication dateSep 18, 2018
Grant dateSep 18, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit device comprising: a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction; a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction; a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line; an insulating film covering the conductive region; and a contact plug extending through the insulating film_from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, the contact plug including, a metal plug, an N-rich metal nitride film on the conductive region, the N-rich metal nitride film surrounding a sidewall and a bottom surface of the metal plug, the N-rich metal nitride film contacting the insulating film around the sidewall of the metal plug, and a metal silicide film between the conductive region and the N-rich metal nitride film. 2. The integrated circuit device according to claim 1 , wherein the N-rich metal nitride film comprises a TiN film. 3. The integrated circuit device according to claim 1 , wherein the sidewall and the bottom surface of the metal plug are in physical contact with the N-rich metal nitride film. 4. The integrated circuit device according to claim 1 , wherein the N-rich metal nitride film is in physical contact with the metal silicide film. 5. The integrated circuit device according to claim 1 , wherein: the at least one fin-shaped active region comprises a fin recess, a bottom of the fin recess being at a level lower than a top surface of the at least one fin-shaped active region under the gate line; and the conductive region comprises a semiconductor layer epitaxially grown on the fin recess. 6. The integrated circuit device according to claim 1 , further comprising: an insulating spacer covering a sidewall of the gate line, the insulating spacer between the gate line and the insulating film. 7. The integrated circuit device according to claim 6 , wherein: the insulating film is interposed between the insulating spacer and the contact plug; and a dielectric constant of the insulating spacer is less than a dielectric constant of the insulating film. 8. The integrated circuit device according to claim 6 , wherein the insulating spacer includes SiOCN, SiCN, SiBN, SiBCN, or combinations thereof. 9. The integrated circuit device according to claim 1 , wherein: the at least one fm-shaped active region comprises a plurality of fin-shaped active regions extending parallel to each other; and the contact plug extends on the plurality of fin-shaped active regions such that the contact plug intersects with the plurality of fin-shaped active regions. 10. The integrated circuit device according to claim 1 , wherein the insulating film includes at least one film selected from among a SiOC film and a SiCOH film. 11. An integrated circuit device comprising: a substrate having at least one active region, the at least one active region extending in a first direction; a gate line extending on the at least one active region in a second direction, the second direction intersecting with the first direction; a source/drain region on the at least one active region at one side of the gate line; an insulating film covering the source/drain region; an interlayer dielectric covering the gate line and the insulating film; and a contact plug extending through the insulating film and the interlayer dielectric from the source/drain region in a third direction, the third direction being perpendicular to a main plane of the substrate, the contact plug including, a metal plug, a metal nitride film on the source/drain region, the metal nitride film surrounding a sidewall and a bottom surface of the metal plug, the metal nitride film contacting the insulating film and the interlayer dielectric around the sidewall of the metal plug, the metal nitride film having a nitrogen content greater than a nitrogen content according to a stoichiometric atomic ratio between metal and nitrogen, and a metal silicide film between the source/drain region and the metal nitride film. 12. The integrated circuit device according to claim 11 , wherein the metal nitride film includes a TiN film. 13. The integrated circuit device according to claim 11 , wherein the sidewall and the bottom surface of the metal plug are in physical contact with the metal nitride film. 14. The integrated circuit device according to claim 11 , wherein the metal nitride film is in physical contact with the metal silicide film. 15. The integrated circuit device according to claim 11 , further comprising: an insulating spacer covering a sidewall of the gate line, the insulating spacer between the gate line and the insulating film. 16. The integrated circuit device according to claim 15 , wherein the insulating film is interposed between the insulating spacer and the contact plug, and wherein a dielectric constant of the insulating spacer is less than a dielectric constant of the insulating film. 17. The integrated circuit device according to claim 15 , wherein the insulating spacer includes SiOCN, SiCN, SiBN, SiBCN, or combinations thereof. 18. The integrated circuit device according to claim 11 , wherein the source/drain region comprises an epitaxially grown semiconductor layer on the at least one active region. 19. The integrated circuit device according to claim 11 , wherein the at least one active region includes a plurality of active regions extending parallel to each other; and the contact plug extends on the plurality of active regions such that the contact plug intersects with the plurality of active regions. 20. The integrated circuit device according to claim 11 , wherein the insulating film includes at least one film selected from among a SiOC film and a SiCOH film.

Assignees

Inventors

Classifications

  • the principal metal being a transition metal · CPC title

  • using conductive layers comprising silicides · CPC title

  • for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title

  • the barrier, adhesion or liner layers being discontinuous · CPC title

  • based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

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What does patent US10079210B2 cover?
An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active regio…
Who is the assignee on this patent?
Samsung Electronics Co Ltd, Samsung Electroics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 18 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).