Light-erasable embedded memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10079204-B2
Application number	US-201715638352-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Apr 28, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

First claim

What is claimed is:

1. A light-erasable embedded memory device, comprising:
a substrate with a memory region and a core circuit region;
a floating gate on said memory region of said substrate;
at least two light-absorbing films above said floating gate over said memory region and said core circuit region, wherein each of said at least two light-absorbing films is provided with at least one dummy via hole overlapping said floating gate; and
at least two dielectric layers, each of which is on each of said at least two light-absorbing films and filling up said at least one dummy via hole.

2. The light-erasable embedded memory device of claim 1 , wherein said at least one dummy via hole of one of said at least two light-absorbing films overlaps said at least one dummy via hole of other said at least two light-absorbing films.

3. The light-erasable embedded memory device of claim 1 , wherein said at least one dummy via hole comprises multiple dummy via holes arranged in an array.

4. The light-erasable embedded memory device of claim 1 , wherein the material of said at least two light-absorbing films is silicon oxynitride (SiON) or silicon nitride (SiN) with relatively low transmission coefficient for UV light.

5. The light-erasable embedded memory device of claim 1 , further comprising an ultra-thick metal on said core circuit region of said substrate, wherein said ultra-thick metal forms in one of said at least two light-absorbing films and in one of said at least two dielectric layers.

6. The light-erasable embedded memory device of claim 1 , wherein the material of one of said at least two dielectric layers is fluorosilicate glass (FSG).

7. The light-erasable embedded memory device of claim 1 , wherein said memory region is a one-time programming (OTP) region.

8. A method of manufacturing a light-erasable embedded memory device, comprising the steps of:
providing a substrate with a memory region and a core circuit region;
forming a floating gate on said memory region of said substrate;
forming at least two light-absorbing films above said floating gate over said memory region and said core circuit region;
forming at least one dummy via hole and via holes concurrently in said at least two light-absorbing films respectively above said memory region and said core circuit region, wherein said at least one dummy via hole overlap said floating gate on said memory region; and
forming at least two dielectric layers respectively over each of said at least two light-absorbing films and filling up said at least one dummy via hole and said via holes.

9. The method of manufacturing a light-erasable embedded memory device of claim 8 , wherein said at least one dummy via hole of one said at least two light-absorbing film overlaps said at least one dummy via hole of other said at least two light-absorbing films.

10. The method of manufacturing a light-erasable embedded memory device of claim 8 , further comprising a step of performing an etch process on said core circuit region to form a recess in said at least two light-absorbing films and said at least two dielectric layers.

11. The method of manufacturing a light-erasable embedded memory device of claim 10 , further comprising a step of filling up said recess in said at least two light-absorbing films and said at least two dielectric layers with metal material to form a metal layer.

12. The method of manufacturing a light-erasable embedded memory device of claim 11 , wherein said metal layer is an ultra-thick metal (UTM).

13. The method of manufacturing a light-erasable embedded memory device of claim 8 , further comprising a step of irradiating UV light passing through said at least one dummy via hole and reaching said floating gate to erase storage data.

14. The method of manufacturing a light-erasable embedded memory device of claim 8 , wherein said memory region is a one-time programming (OTP) region.

Assignees

• United Microelectronics Corp

Inventors

• Su Hao
• Lim Chow Yee
• Jiang Chao
• Liao Hong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G11C16/0433 Primary

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• H01L23/5226 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic