Methods and apparatus for running and booting an inter-processor communication link between independently operable processors

Patent metadata

Field	Value
Publication number	US-10078361-B2
Application number	US-201514879024-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Oct 8, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

First claim

What is claimed is:

1. Processor apparatus, comprising:
a first digital processor apparatus;
a physical bus interface in data communication with the first digital processor apparatus; and
a computer readable medium in data communication with the first digital processor apparatus and comprising one or more computer readable instructions, the one or more computer readable instructions configured to, when executed by the first digital processor apparatus, cause the first digital processor apparatus to:
determine whether a second digital processor apparatus in data communication with the first digital processor apparatus is in a first boot sequence, the first boot sequence being executable by the second digital processor apparatus; and
when it is determined that the second digital processor is in the first boot sequence, transmit a second boot stage image to the second digital processor apparatus via at least the physical bus interface, the second boot stage image being different from a first boot stage image executed in the first boot sequence prior to the transmission of the second boot stage image.

2. The processor apparatus of claim 1 , wherein:
the processor apparatus comprises a host processor apparatus, the physical bus interface comprises an inter-processor communication (IPC) interface, the second digital processor apparatus comprises a peripheral component; and
the transmission is configured to cause the peripheral component, responsive to receiving the second boot stage image, to complete a boot sequence.

3. The processor apparatus of claim 2 , wherein the processor apparatus comprises an integrated circuit (IC), the IC having at least the first digital processor and the physical bus interface substantially contained therein.

4. The processor apparatus of claim 2 , wherein the processor apparatus comprises a chipset comprising a plurality of integrated circuits (ICs), respective ones of the plurality of ICs having the first digital processor apparatus and the physical bus interface associated therewith.

5. The processor apparatus of claim 2 , wherein the processor apparatus comprises an application processor (AP) integrated circuit (IC), and the second digital processor apparatus of the peripheral component comprises a wireless baseband (BB) digital processor.

6. The processor apparatus of claim 1 , wherein the second digital processor apparatus comprises a peripheral processing apparatus that does not have a complete boot image stored thereon.

7. Processor apparatus, comprising:
a first digital processor apparatus;
a physical bus interface in data communication with the first digital processor apparatus; and
a computer readable medium in data communication with the first digital processor apparatus and comprising one or more computer readable instructions, the one or more computer readable instructions configured to, when executed by the first digital processor apparatus:
cause the first digital processor apparatus to execute a primary boot sequence using a primary boot stage image, the execution of the primary boot sequence configured to cause a digital processor apparatus other than the first digital processor apparatus to (i) generate a secondary boot stage image that is distinct from the primary boot stage image, the secondary boot stage image being generated based on a selection from a plurality of boot stage images corresponding to a plurality of capabilities of the first digital processor apparatus, and (ii) cause transfer of the secondary boot stage image to the first digital processor apparatus; and
responsive to receipt of the secondary boot stage image, execute the secondary boot stage image on the first digital processor apparatus.

8. The processor apparatus of claim 7 , wherein the causation of the digital processor apparatus other than the first digital processor apparatus to generate the secondary boot stage image comprises transmission of a communication from the first digital processor apparatus to the other digital processor apparatus via at least the physical bus interface.

9. The processor apparatus of claim 7 , wherein the processor apparatus comprises an integrated circuit (IC), the IC having at least the first digital processor apparatus and the physical bus interface substantially rendered in integrated circuitry therein on a common semiconductive die.

10. The processor apparatus of claim 7 , wherein the processor apparatus comprises a chipset comprising a plurality of integrated circuits (ICs), respective ones of the plurality of ICs having the first digital processor apparatus and the physical bus interface associated therewith.

11. The processor apparatus of claim 7 , wherein the processor apparatus comprises a wireless baseband (BB) digital processor apparatus, and the digital processor apparatus other than the first digital processor apparatus comprises an application processor (AP) integrated circuit (IC).

12. The processor apparatus of claim 11 , wherein the wireless BB digital processor apparatus is disposed in a second IC comprising a separate semiconductive die from a die of the AP IC.

13. A method of initialization in a computerized apparatus, the method comprising:
executing on a first digital processor at least one computer program comprising a boot sequence based on a primary boot stage image;
based at least in part on the executing, causing a digital processor other than the first digital processor to (i) generate a secondary boot stage image, and (ii) transfer the secondary boot stage image to the first digital processor;
receiving the secondary boot stage image; and
executing the secondary boot stage image on the first digital processor.

14. The method of claim 13 , wherein the first digital processor is associated with a host device, and the method further comprises operating, subsequent to the executing of the secondary boot stage image, the host device based at least in part on the executed secondary boot image.

15. The method of claim 13 , further comprising:
establishing an inter-processor communication link between at least the first digital processor and the digital processor other than the first digital processor; and
wherein the causing comprises transmitting one or more communications via the inter-processor communication link from the first digital processor to the digital processor other than the first digital processor, the one or more communications transmitted at least after the executing of the at least one computer program has commenced.

16. The method of claim 15 , wherein:
the transmitting of the one or more communications from the first digital processor to the digital processor other than the first digital processor comprises transmitting the one or more communications between a first region of a single-die system-on-chip (SoC) integrated circuit (IC) and a second region of the SoC IC; and
the inter-processor communication link comprises a plurality of individual data lanes or wires formed on the SoC IC collectively upon which the one or more communications can be carried.

17. The method of claim 15 , wherein:
the transmitting of the one or more communications from the first digital processor to the digital processor other than the first digital processor comprises transmitting the one or more communications between a first integrated circuit (IC) and a second, physically separate IC; and
the inter-processor communication link comprises a plurality of individual data lanes or wires formed on at least the first IC collectively upon which the one or more communications can be carried, the o

Assignees

• Apple Inc

Inventors

• Sanghi Karan
• Garg Saurabh
• Zhang Haining

Classifications

• G06F9/4403

  Processor initialisation · CPC title

• G06F9/4405

  Initialisation of multiprocessor systems · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F11/1417

  Boot up procedures · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title