Processor core power event tracing

Patent metadata

Field	Value
Publication number	US-9910475-B2
Application number	US-201414580553-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

First claim

What is claimed is:

1. A processor, comprising:
a processor core; and
a trace unit, including circuitry to:
monitor activity by the processor core and generate trace packets indicative of the activity by the processor core; and
generate a dormant state request packet to indicate that the processor core received a power management request for a first dormant state in a wake state, wherein the dormant state request packet includes an indication of the first dormant state; and
generate a code execution stop packet to indicate that the processor core stopped execution of code, wherein the code execution stop packet identifies an instruction pointer address of a processor instruction that did not complete when the code execution stop packet was generated.

2. The processor of claim 1 , further comprising:
a front end including circuitry to receive the power management request as a software instruction to the processor core, wherein the dormant state request packet includes an indication of the software instruction.

3. The processor of claim 1 , wherein the trace unit further includes circuitry to:
generate a dormant state entry packet to indicate that the processor core entered a second dormant state.

4. The processor of claim 1 , wherein the code execution stop packet is to be generated in response to a clock frequency modulation event, wherein the processor core remains in a wake state in the clock frequency event.

5. The processor of claim 1 , wherein:
the circuitry to generate a code execution stop packet is to generate the code execution stop packet in response to the power management request; and
the circuitry to generate a dormant state entry packet is to generate the dormant state entry packet in response to the power management request.

6. The processor of claim 3 , wherein the first dormant state is the second dormant state.

7. The processor of claim 3 , wherein:
the trace unit further includes circuitry to generate a dormant state exit packet to indicate that the processor core returned to the wake state; and
the processor further includes a trace configuration register accessible to the trace unit, the trace configuration register to enable activation, independently from other trace packets, of generation of the dormant state request packet, the code execution stop packet, the dormant state entry packet, and the dormant state exit packet.

8. A method comprising, within a processor:
generating, by a processor trace unit for monitoring activity by a processor core included within the processor, trace packets indicative of the activity by the processor core, wherein the trace packets include:
a dormant state request packet indicating that the processor core received a power management request for a first dormant state during a wake state, wherein the dormant state request packet includes an indication of the first dormant state; and
a code execution stop packet to indicating that the processor core stopped execution of code, wherein the code execution stop packet identifies an instruction pointer address of a processor instruction that did not complete when the code execution stop packet was generated.

9. The method of claim 8 , further comprising:
receiving the power management request as a software instruction to the processor core, wherein the dormant state request packet includes an indication of the software instruction.

10. The method of claim 8 , wherein the trace packets include:
a dormant state entry packet indicating that the processor core entered the first dormant state; and
a dormant state exit packet indicating that the processor core returned to the wake state.

11. The method of claim 8 , wherein the code execution stop packet is generated in response to a clock frequency modulation event, wherein the processor core remains in a wake state during the clock frequency event.

12. The method of claim 10 , further comprising:
prior to generating the trace packets, setting a trace configuration register for activating, independently from other trace packets, generation of the dormant state request packet, the code execution stop packet, the dormant state entry packet, and the dormant state exit packet.

13. A system, comprising:
a processor including a processor core; and
a trace unit including circuitry to:
monitor activity by the processor core and generate trace packets indicative of the activity by the processor core;
generate a dormant state request packet to indicate that the processor core received a power management request for a first dormant state in a wake state, wherein the dormant state request packet includes an indication of the first dormant state; and
generate a code execution stop packet to indicate that the processor core stopped execution of code, wherein the code execution stop packet identifies an instruction pointer address of a processor instruction that did not complete when the code execution stop packet was generated.

14. The system of claim 13 , further comprising:
a front end including circuitry to receive the power management request as a software instruction to the processor core, wherein the dormant state request packet includes an indication of the software instruction.

15. The system of claim 13 , wherein the trace unit further includes circuitry to:
generate a dormant state entry packet to indicate that the processor core entered a second dormant state.

16. The system of claim 13 , wherein the code execution stop packet is to be generated in response to a clock frequency modulation event, wherein the processor core remains in a wake state in the clock frequency event.

17. The system of claim 15 , wherein:
the circuitry to generate a code execution stop packet is to generate the code execution stop packet in response to the power management request; and
the circuitry to generate a code execution stop packet is to generate the dormant state entry packet in response to the power management request.

18. The system of claim 15 , wherein the first dormant state is the second dormant state.

19. The system of claim 15 , wherein:
the trace unit further includes circuitry to generate a dormant state exit packet to indicate that the processor core returned to the wake state; and
the processor includes a trace configuration register accessible to the trace unit, the trace configuration register to enable activation, independently from other trace packets, of generation of the dormant state request packet, the code execution stop packet, the dormant state entry packet, and the dormant state exit packet.

Assignees

• Intel Corp

Inventors

• Kurts Tsvika
• Strong Beeman C
• Oconnor Richard B
• Chynoweth Michael W
• Chabukswar Rajshree A
• Lottem Avner
• Kazachinsky Itamar
• Mishaeli Michael
• Wojciechowski Anthony
• Vasisht Vikas R

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/3055

  Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16) · CPC title