Implementing backdrilling elimination utilizing anti-electroplate coating

Patent metadata

Field	Value
Publication number	US-10076045-B2
Application number	US-201715722519-A
Country	US
Kind code	B2
Filing date	Oct 2, 2017
Priority date	Jul 22, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill vias during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a plug is inserted into each via and the plug is lowered to a depth just below a desired signal trace layer. A thin anti-electroplate coating is applied onto the walls of the via below the signal trace. Then the plugs are removed and a standard board plating process for the PCB is performed.

First claim

What is claimed is:

1. A method for implementing enhanced via creation without creating a via barrel stub during printed circuit board (PCB) manufacturing comprising:
providing a printed circuit board (PCB); said printed circuit board (PCB) having an internal conductive trace;
forming a via extending through the printed circuit board (PCB) including the internal conductive trace; and
inserting a plug into the via extending from a first surface to below the internal conductive trace;
applying an anti-electroplate coating covering the walls of the via below the signal trace; said anti-electroplate coating eliminating via barrel stub creation during the PCB manufacturing; and
removing the plug and performing PCB plating.

2. The method as recited in claim 1 wherein applying an anti-electroplate coating covering the walls of the via below the signal trace includes applying said anti-electroplate coating by vapor deposition.

3. The method as recited in claim 1 wherein applying an anti-electroplate coating covering the walls of the via below the signal trace includes applying said anti-electroplate coating having a selected thickness in a range between 0.2 μm and 0.5 μm.

4. The method as recited in claim 1 wherein applying an anti-electroplate coating covering the walls of the via below the signal trace includes applying said anti-electroplate coating formed of a chemically resistant polymer.

5. The method as recited in claim 1 wherein applying an anti-electroplate coating covering the walls of the via below the signal trace includes applying said anti-electroplate coating formed of a hydrophobic polymer.

6. The method as recited in claim 1 wherein applying an anti-electroplate coating covering the walls of the via below the signal trace includes applying said anti-electroplate coating formed of polytetrafluoroethylene (PTFE).

7. The method as recited in claim 6 includes applying said polytetrafluoroethylene (PTFE) coating by vapor deposition.

8. The method as recited in claim 6 includes applying said polytetrafluoroethylene (PTFE) coating having a selected thickness in a range between 0.2 μm and 0.5 μm.

9. The method as recited in claim 1 wherein providing a printed circuit board (PCB); said printed circuit board (PCB) having an internal conductive trace includes a standard PCB manufacturing process.

10. The method as recited in claim 1 wherein inserting a plug into the via from a top surface extending below the internal conductive trace includes said plug blocking said anti-electroplate coating being applied to said internal conductive trace.

11. The method as recited in claim 1 wherein a standard PCB plating process is performed responsive to removing the plug.

12. The method as recited in claim 1 wherein eliminating via back-drilling enables improved yield and reliability of the PCB.

13. A printed circuit board (PCB) structure produced by a method as recited in claim 1 .

Assignees

• IBM

Inventors

• Doyle Matthew S
• Kuczynski Joseph
• Mann Phillip V
• O'Connell Kevin M

Classifications

• H05K1/034

  containing halogen · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K2201/015

  Fluoropolymer, e.g. polytetrafluoroethylene [PTFE] · CPC title

• H05K3/423

  characterised by electroplating method · CPC title

• H05K2203/143

  Treating holes before another process, e.g. coating holes before coating the substrate · CPC title