Signal isolator integrated circuit package

Patent metadata

Field	Value
Publication number	US-10074713-B1
Application number	US-201715705487-A
Country	US
Kind code	B1
Filing date	Sep 15, 2017
Priority date	Sep 15, 2017
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A signal isolator integrated circuit package includes a first die in a first voltage domain and a second die in a second voltage domain. The integrated circuit package also includes a first signal path from the first die to the second die via a first isolation barrier supported by the first die. The first isolation barrier includes a first conductive layer disposed over a surface of the first die and a first insulating layer disposed over the first conductive layer. The first isolation barrier also includes a second insulating layer disposed over the first insulating layer and a second conductive layer disposed over the second insulating layer. A first floating conductive plate is disposed between the first insulating layer and the second insulating layer.

First claim

What is claimed is:

1. A signal isolator integrated circuit package, comprising:
a first die in a first voltage domain;
a second die in a second voltage domain, wherein the first and second die are galvanically isolated; and
a first signal path from the first die to the second die via a first isolation barrier supported by the first die, the first isolation barrier comprising:
a first conductive layer disposed over a surface of the first die;
a first insulating layer disposed over the first conductive layer;
a second insulating layer disposed over the first insulating layer;
a second conductive layer disposed over the second insulating layer; and
a first floating conductive plate disposed between the first insulating layer and the second insulating layer.

2. The integrated circuit package according to claim 1 , wherein at least one edge of the first floating conductive plate extends beyond an edge of the first conductive layer to increase evenness of electric charge distribution.

3. The integrated circuit package according to claim 1 , wherein the first insulating layer and the second insulating layer each have a respective thickness, and the thickness of at least one of the first insulating layer and the second insulating layer is selected to provide a first predetermined level of signal isolation between the first die and the second die.

4. The integrated circuit package according to claim 1 , wherein the first insulating layer and the second insulating layer have a substantially similar thickness.

5. The integrated circuit package according to claim 1 , wherein at least one of the first insulating layer and the second insulating layer comprises a plurality of layers including one or more insulating materials.

6. The integrated circuit package according to claim 1 , wherein the first conductive layer and the second conductive layer each have a respective thickness, and the thickness of at least one of the first conductive layer and the second conductive layer is selected to provide a first predetermined level of signal isolation between the first die and the second die.

7. The integrated circuit package according to claim 1 , wherein the first floating conductive plate is spaced substantially equidistant from the first conductive layer and the second conductive layer.

8. The integrated circuit package according to claim 1 , wherein the first signal path comprises one or more wirebonds.

9. The integrated circuit package according to claim 1 , wherein the second die has a first die area in the second voltage domain and a second die area in a third voltage domain, and the integrated circuit package further comprises: a second signal path from the first die area to the second die area via a second isolation barrier supported by the second die, the second isolation barrier comprising:
a third conductive layer disposed over a surface of the second die;
a third insulating layer disposed over the third conductive layer; and
a fourth conductive layer disposed over the third insulating layer.

10. The integrated circuit package according to claim 9 , wherein the second isolation barrier further comprises:
a second floating conductive plate disposed between the third insulating layer and the fourth conductive layer; and
a fourth insulating layer disposed between the second floating conductive plate and the fourth conductive layer.

11. The integrated circuit package according to claim 10 , wherein the third insulating layer and the fourth insulating layer each have a respective thickness, and the thickness of at least one of the third insulating layer and the fourth insulating layer is selected to provide a second predetermined level of signal isolation between the first die area and the second die area.

12. The integrated circuit package according to claim 10 , wherein the second floating conductive plate is spaced substantially equidistant from the third conductive layer and the fourth conductive layer.

13. The integrated circuit package according to claim 9 , wherein the third conductive layer and the fourth conductive layer each have a respective thickness, and the thickness of at least one of the third conductive layer and the fourth conductive layer is selected to provide a second predetermined level of signal isolation between the first die area and the second die area.

14. A signal isolator integrated circuit package, comprising:
a first die having a first die area in a first voltage domain and a second die area in a second voltage domain, wherein the first and second die areas are galvanically isolated; and
a first signal path from the first die area to the second die area via a first isolation barrier supported by the first die, the first isolation barrier comprising:
a first conductive layer disposed over a surface of the first die;
a first insulating layer disposed over the first conductive layer;
a second insulating layer disposed over the first insulating layer;
a second conductive layer disposed over the second insulating layer; and
a first floating conductive plate disposed between the first insulating layer and the second insulating layer.

15. The integrated circuit package according to claim 14 , wherein at least one edge of the first floating conductive plate extends beyond an edge of the first conductive layer to increase evenness of electric charge distribution.

16. The integrated circuit package according to claim 14 , wherein the first insulating layer and the second insulating layer each have a respective thickness, and the thickness of at least one of the first insulating layer and the second insulating layer is selected to provide a first predetermined level of signal isolation between the first die area and the second die area.

17. The integrated circuit package according to claim 14 , wherein the first conductive layer and the second conductive layer each have a respective thickness, and the thickness of at least one of the first conductive layer and the second conductive layer is selected to provide a first predetermined level of signal isolation between the first die area and the second die area.

18. The integrated circuit package according to claim 14 , wherein the first floating conductive plate is spaced substantially equidistant from the first conductive layer and the second conductive layer.

19. The integrated circuit package according to claim 14 , further comprising:
a second die in a third voltage domain, wherein the first and second die are galvanically isolated; and
a second signal path from the second die area of the first die to the second die via a second isolation barrier supported by one of the first die and the second die, the second isolation barrier comprising:
a third conductive layer disposed over a surface of the second die;
a third insulating layer disposed over the third conductive layer;
a fourth insulating layer disposed over the third insulating layer;
a fourth conductive layer disposed over the fourth insulating layer; and
a second floating conductive plate disposed between the third insulating layer and the fourth insulating layer.

20. The integrated circuit package according to claim 19 , wherein the third insulating layer and the fourth insulating layer each have a respective thickness, and the thickness of at least one of the third insulating layer and the fourth insulating layer is selected to provide a second predetermined level of signal isolation between the first die area and the second die area.

Assignees

• Allegro Microsystems Llc

Inventors

• Briano Robert A

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/758

  between a chip and a stacked discrete passive device · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title