Isolator integrated circuits with package structure cavity and fabrication methods

Patent metadata

Field	Value
Publication number	US-10074639-B2
Application number	US-201615395584-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Disclosed examples include integrated circuits with a leadframe structure, a first circuit structure including a light source configured to generate a light signal along an optical path, a second circuit structure including a light sensor facing the optical path to receive the light signal, and a molded package structure enclosing portions of the leadframe structure, the molded package structure having a cavity defined by an interior surface of the molded package structure, the optical path extending in the cavity between the first and second circuit structures.

First claim

The following is claimed:

1. An integrated circuit (IC), comprising:
a leadframe structure, including a plurality of electrical conductors;
a first circuit structure electrically connected to a first pair of the electrical conductors of the leadframe structure, the first circuit structure including a light source configured to generate a light signal;
a second circuit structure spaced from the first circuit structure and electrically connected to a second pair of the electrical conductors of the leadframe structure, the second circuit structure including a light sensor at least partially facing the light source to receive the light signal; and
a molded package structure enclosing portions of the leadframe structure, the molded package structure exposing portions of the first and second pairs of the electrical conductors to allow external connection to the first and second circuit structures, the molded package structure including an internal cavity defined by an interior surface of the molded package structure, the cavity providing a solid-free optical path for the light signal between the first and second circuit structures, the optical path extending in a direction corresponding to a straight line extending directly from the first circuit structure to the second circuit structure.

2. The IC of claim 1 , wherein the cavity is sealed.

3. The IC of claim 1 , wherein the interior surface of the molded package structure includes a concave portion, and wherein the concave portion of the interior surface includes a reflective coating to reflect light from the light source toward the light sensor.

4. The IC of claim 1 , wherein the light source includes a light emitting diode (LED).

5. The IC of claim 1 , wherein the light sensor includes a diode.

6. The IC of claim 5 , wherein the light sensor includes a plurality of diodes.

7. The IC of claim 6 , wherein the light sensor includes a plurality of connected diodes, individual ones of the plurality of diodes including N and P regions of a semiconductor die arranged along the optical path.

8. The IC of claim 6 , wherein the light sensor includes a plurality of connected diodes, individual ones of the plurality of diodes including N and P regions of a semiconductor die arranged normal to the optical path.

9. The IC of claim 1 , wherein the light sensor includes a transistor.

10. The IC of claim 1 , wherein the molded package structure encloses portions of the first and second circuit structures.

11. A method to fabricate an integrated circuit (IC), the method comprising:
mounting at least one semiconductor die on a leadframe structure;
connecting a plurality of bond wires between bond pads of the semiconductor die and corresponding electrical conductors of the leadframe structure;
forming a sacrificial material over a portion of the semiconductor die;
forming a molded package material over the semiconductor die, the bond wires and portions of the leadframe structure and the sacrificial material to create a molded package structure; and
sublimating the sacrificial material to create an internal cavity defined by an interior surface of the molded package structure, the internal cavity including at least a portion of an isolation barrier between first and second circuit structures, at least one of the first or second circuit structures associated with the semiconductor die, the first circuit structure electrically connected to a first pair of the electrical conductors of the leadframe structure, the first circuit structure including a light source configured to generate a light signal, the second circuit structure spaced from the first circuit structure and electrically connected to a second pair of the electrical conductors of the leadframe structure, the second circuit structure including a light sensor at least partially facing the light source to receive the light signal, the molded package structure exposing portions of the first and second pairs of the electrical conductors to allow external connection to the first and second circuit structures, the cavity providing a solid-free optical path for the light signal between the first and second circuit structures, the optical path extending in a direction corresponding to a straight line extending directly from the first circuit structure to the second circuit structure.

12. The method of claim 11 , further including sealing the internal cavity.

13. The method of claim 11 , further including:
mounting a first semiconductor die on the leadframe structure, the first semiconductor die including the light source configured to generate the light signal along the optical path;
mounting a second semiconductor die on the leadframe structure, the second semiconductor die including the light sensor at least partially facing the optical path and spaced from the light source of the first semiconductor die to receive the light signal;
connecting die pads of the first semiconductor die to the first pair of the electrical conductors of the leadframe structure;
connecting die pads of the second semiconductor die to the second pair of the electrical conductors of the leadframe structure; and
forming the sacrificial material over a portion of the first and second semiconductor dies at least partially along the optical path;
wherein sublimating the sacrificial material creates the internal cavity including at least a portion of the optical path to allow transmission of the light signal between the light source and the light sensor.

14. The method of claim 13 , wherein the sacrificial material is formed as a drop having a convex surface, the method further including:
forming a reflective coating on the convex surface of the sacrificial material; and
forming the molded package material on the reflective coating.

15. The IC of claim 1 , wherein the interior surface of the molded package structure includes a concave surface that extends from a first surface of the first circuit structure to a second surface of the second circuit structure.

16. The IC of claim 15 , wherein the first surface is a top surface of the first circuit structure and the second surface is a top surface of the second circuit structure such that portions of the top surfaces of the first and second circuit structures are exposed within the cavity.

17. The IC of claim 15 , wherein the first surface is a side surface of the first circuit structure and the second surface is a side surface of the second circuit structure such that top surfaces of the first and second circuit structures are encapsulated by the molded package structure.

18. The IC of claim 1 , wherein the first circuit structure is electrically connected to the first pair of the electrical conductors via bond wires, the bond wires being encapsulated within the molded package structure.

19. The IC of claim 1 , wherein the first circuit structure has a top surface facing away from the leadframe structure, at least a portion of the top surface being encapsulated within the molded package structure.

Assignees

• Texas Instruments Inc

Inventors

• Male Barry Jon
• Cook Benjamin
• Neidorff Robert Alan
• Kummerl Steve

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/075

  of bond wires · CPC title