Method of manufacturing interposer-based damping resistor

Patent metadata

Field	Value
Publication number	US-10074600-B2
Application number	US-201213436150-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

First claim

What is claimed is:

1. A method of manufacturing, comprising:
forming a resistor onboard an interposer, the interposer adapted to have a first semiconductor chip mounted thereon, the resistor adapted to dampen a capacitive network, the capacitive network having at least one capacitor positioned off the interposer and the first semiconductor chip.

2. The method of claim 1 , comprising coupling a circuit board to the interposer and the at least one capacitor to the circuit board.

3. The method of claim 1 , wherein the forming a resistor comprises fabricating a conductor line and a first through-silicon-via coupled to the conductor line.

4. The method of claim 3 , wherein the forming the resistor comprises fabricating a second through-silicon-via coupled to the conductor line, the first and second through-silicon-vias and the conductor line being connected in series.

5. The method of claim 1 , comprising coupling the first semiconductor chip to the interposer.

6. The method of claim 5 , comprising coupling a second semiconductor chip to the interposer.

7. The method of claim 1 , comprising coupling the onboard resistor between a power network and a ground.

8. A method of manufacturing, comprising:
forming a resistor onboard an interposer, the interposer adapted to have a first semiconductor chip mounted thereon, the resistor having a resistance selected to provide a desired level of damping for a capacitive network, the capacitive network having at least one capacitor positioned off the interposer and the first semiconductor chip.

9. The method of claim 8 , comprising coupling a circuit board to the interposer and the at least one capacitor to the circuit board.

10. The method of claim 8 , wherein the forming a resistor comprises fabricating a conductor line and a first through-silicon-via coupled to the conductor line.

11. The method of claim 8 , comprising coupling the first semiconductor chip to the interposer.

12. The method of claim 11 , comprising coupling a second semiconductor chip to the interposer.

13. The method of claim 12 , wherein the second semiconductor chip is stacked on the first semiconductor chip.

14. The method of claim 12 , wherein the second semiconductor chip is positioned lateral to the first semiconductor chip.

Assignees

• Guo Fei
• Zhu Feng
• Din Julius
• Kashem Anwar
• Yeung Sally
• Ati Technologies Ulc
• Advanced Micro Devices Inc

Inventors

• Guo Fei
• Zhu Feng
• Din Julius
• Kashem Anwar
• Yeung Sally

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• Y10T29/4913

  Assembling to base an electrical component, e.g., capacitor, etc. · CPC title