Method for producing a component
US-9156058-B2 · Oct 13, 2015 · US
US10074589B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10074589-B2 |
| Application number | US-201615098597-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 14, 2016 |
| Priority date | Apr 14, 2016 |
| Publication date | Sep 11, 2018 |
| Grant date | Sep 11, 2018 |
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A multi-layer structure includes a substrate with a surface and with particles partially covering and partially embedded in the surface. The particles have high thermal conductivity and low electrical conductivity. A dielectric layer on the surface partially covers the partially embedded particles. A metal layer on the dielectric layer covering the partially covered particles forms a thermal interface material (TIM) for electronic packaging applications.
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The invention claimed is: 1. A method of forming a multi-layer thermal interface structure with a high thermal conductivity and low electrical conductivity on a metal substrate comprising: partially covering a top surface of the metal substrate with high thermal conductivity, low electrical conductivity particles; partially melting the top surface of the metal substrate, thereby causing the particles to sink into the molten metal layer; allowing the molten metal layer to solidify to partially embed the particles in the solidified metal layer; partially covering the space around the partially embedded particles and partially covering the partially embedded particles with a polymeric dielectric material; and covering the partially covered particles and the polymeric dielectric material with a metal top layer. 2. The method of claim 1 , wherein the high thermal conductivity, low electrical conductivity particles are composed of diamond, boron nitride, silicon nitride or silicon carbide. 3. The method of claim 1 , wherein the high thermal conductivity, low electrical conductivity particles have a diameter of from 1 micron to 100 microns. 4. The method of claim 1 , wherein the surface coverage of the high thermal conductivity, low electrical conductivity particles on the substrate is from about 20% to about 90%. 5. The method of claim 4 , wherein the surface coverage of the high thermal conductivity, low electrical conductivity particles on the substrate is from about 30% to about 75%. 6. The method of claim 1 , wherein the metal substrate comprises nickel, titanium, aluminum, copper, cobalt, tungsten, or alloys thereof, or mixtures thereof. 7. The method of claim 6 , wherein the metal substrate is a nickel alloy. 8. The method of claim 1 , wherein partially melting the top surface of the substrate comprises laser melting, RF induction melting, infrared melting, electric arc melting or plasma melting. 9. The method of claim 1 , wherein the polymeric dielectric material is a polyimide, polyethylene, nylon, spin on glass, or polyester. 10. The method of claim 1 , wherein the polymeric dielectric material is a polymer with electrical resistivity greater than 10 6 ohm-cm. 11. The method of claim 1 , wherein partially covering a top surface of the substrate with high thermal conductivity, low electrical conductivity particles and partially melting the top surface of the substrate comprises an additive manufacturing process. 12. The method of claim 11 , wherein the additive manufacturing process comprises laser engineered net shaping (LENS), direct light manufacturing, selective laser melting (SLM), direct laser melting (DLM), laser based additive manufacturing (LBAM), or radio frequency induction melting.
of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title
Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title
Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title
Diamond · CPC title
Organics · CPC title
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