Method of initializing and programing 3D non-volatile memory device

Patent metadata

Field	Value
Publication number	US-10074435-B2
Application number	US-201815916097-A
Country	US
Kind code	B2
Filing date	Mar 8, 2018
Priority date	Nov 5, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selection transistors.

First claim

What is claimed is:

1. A method of initializing a 3D non-volatile memory device, the 3D non-volatile memory device comprising a plurality of string selection lines, a plurality of wordlines, a dummy ground line, a ground selection line, and a plurality of memory layers, each of the memory layers comprising a plurality of channel lines respectively coupled to a plurality of bitlines via first ends of the plurality of channel lines and coupled to a common source line of the memory layer via second ends of the plurality of channel lines, wherein the plurality of string selection lines, the plurality of wordlines, the dummy ground line and the ground selection line intersect with the plurality of channel lines, and each of the plurality of channel lines defines a memory string, the method comprising,
applying a first program voltage to a selected string selection line in a selected memory layer among the plurality of memory layers;
verifying whether threshold voltages of a plurality of string selection transistors coupled with the selected string selection line reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors;
applying a voltage equal to or higher than a common collector voltage to first bitlines coupled with the unprogrammed string selection transistors, applying a ground voltage to second bitlines coupled with the programmed string selection transistors, and applying a second program voltage to the dummy ground line, thereby inducing channel potential boosting at memory strings respectively coupled with the unprogrammed string selection transistors, such that dummy ground transistor in memory strings respectively coupled with the programmed string selection transistors is programmed to have a predetermined threshold voltage and dummy ground transistor in the first memory strings are not programmed; and
selectively programming the unprogrammed string selection transistors by turning the programmed dummy ground transistors off and applying a third program voltage to the selected string selection line.

2. The method of claim 1 , wherein applying the first program voltage, verifying whether the threshold voltages of the plurality of string selection transistors reach the target value, and selectively programming the unprogrammed string selection transistors respectively include performing an incremental step pulse programming (ISPP) technique.

3. The method of claim 1 , wherein the plurality of selection transistors coupled with the selected string selection line is a first plurality of string selection transistors, the method further comprising, before applying the first program voltage is performed, erasing a second plurality of string selection transistors coupled with the plurality of string selection lines and a plurality of dummy ground transistors coupled with the dummy ground line, the second plurality of string selection transistors including the first plurality of string selection transistors.

4. The method of claim 1 , wherein verifying whether the threshold voltages of the plurality of string selection transistors reach the target value includes:
applying a sensing voltage is applied to the plurality of bitlines; and
applying a voltage substantially equal to the sensing voltage is to common source lines of the unselected memory layers among the plurality of memory layers.

5. The method of claim 1 , wherein selectively programming the unprogrammed string selection transistors includes applying a ground voltage to a common source line of the selected memory layer, applying a common collector voltage to common source lines of the unselected memory layers among the plurality of memory layers and to the plurality of bitlines to float channel lines of memory strings of the unselected memory layers.

6. The method of claim 1 , wherein the 3D non-volatile memory device has a channel stacked structure, a straight-shaped bit cost scalable (BiCs) structure, a pipe-shaped BiCs structure, or a combination thereof.

7. The method of claim 1 , wherein the 3D non-volatile memory device is a NAND flash memory device.

Assignees

• Sk Hynix Inc
• Seoul Nat Univ R&Db Foundation

Inventors

• Park Byung Gook
• Kwon Dae Woong
• Kim Do Bin
• Lee Sang Ho

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title