SRAM module and writing control method thereof

Patent metadata

Field	Value
Publication number	US-10074418-B2
Application number	US-201715836922-A
Country	US
Kind code	B2
Filing date	Dec 11, 2017
Priority date	Feb 6, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

First claim

What is claimed is:

1. An SRAM module, the SRAM module having a plurality of memory cells, comprising:
a bit line, coupled to the memory cells, for transmitting a write data;
an actuating unit, coupled to the bit line, for providing a first voltage level as a supply voltage to the memory cells during a data retention time of the memory cells; and
a voltage decreasing unit, coupled to the bit line, for decreasing the first voltage level corresponding to data retention of the memory cells to a second voltage level by discharging the memory cells;
wherein, a discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

2. The SRAM module of claim 1 further comprising:
a capacitor, coupled to the bit line, wherein the voltage decreasing unit, coupled the capacitor, for generating a voltage difference on the capacitor, thereby to couple the voltage difference to the bit line to cause a voltage drop.

3. The SRAM module of claim 2 , wherein the magnitude of the voltage difference is directly proportional to the number of the memory cells.

4. The SRAM module of claim 2 , wherein an end of the capacitor is coupled to the bit line, and the voltage decreasing unit is utilized to couple the other end of the capacitor to ground according to a reset signal, thereby to cause the voltage drop on the bit line.

5. The SRAM module of claim 1 , wherein the discharge time from the first voltage level to the second voltage level is directly proportional to the number of the memory cells.

6. The SRAM module of claim 5 , wherein a voltage difference between the first voltage level and the second voltage level is a predetermined value, which is irrelevant to the number of the memory cells.

7. The SRAM module of claim 1 , wherein the actuating unit stops providing the first voltage level to the memory cells before the voltage decreasing unit decreases the first voltage level.

8. A writing control method of an SRAM module, the SRAM module having a plurality of memory cells and a bit line, the writing control method comprising:
providing a first voltage level as a supply voltage to the memory cells during a data retention time of the memory cells;
decreasing the first voltage level corresponding to data retention of the memory cells to a second voltage level by discharging the memory cells; and
performing a write procedure to the memory cells through the bit line;
wherein, a discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

9. The writing control method of claim 8 further comprising:
generating a voltage difference and using a capacitor to couple the voltage difference to the bit line to cause a voltage drop on the bit line.

10. The writing control method of claim 9 , wherein the magnitude of the voltage difference is directly proportional to the number of the memory cells.

11. The writing control method of claim 9 , wherein an end of the capacitor is coupled to the bit line, and the step of generating the voltage drop is to couple the other end of the capacitor to ground according to a reset signal.

12. The writing control method of claim 8 , wherein the discharge time from the first voltage level to the second voltage level is directly proportional to the number of the memory cells.

13. The writing control method of claim 12 , wherein a voltage difference between the first voltage level and the second voltage level is a predetermined value, which is irrelevant to the number of the memory cells.

14. The writing control method of claim 1 further comprising:
stopping providing the first voltage level to the memory cells before decreasing the first voltage level.

15. An SRAM module, the SRAM module having a plurality of memory cells and a bit line, the SRAM module comprising:
a signal generator, for generating an enable signal;
a detection unit, for generating a control signal according to a characteristic value related to the number of the memory cells;
a voltage difference generator, for generating a voltage difference according to the enable signal and the control signal; and
a capacitor, for applying the voltage difference to the bit line to cause a voltage drop on the bit line.

16. The SRAM module of claim 15 , wherein the capacitor is utilized for applying a voltage to the memory cells in order that the memory cells have a voltage level by which the memory cells retain data stored therein; the detection unit is utilized for stopping applying the voltage to the memory cells according to the enable signal; and the voltage difference generator is utilized for decreasing the voltage level of the memory cells according to the enable signal and generating the control signal according to a change in the voltage level.

17. The SRAM module of claim 15 , wherein a magnitude of the voltage drop is directly proportional to the number of the memory cells.

18. A writing control method of an SRAM module, the SRAM module having a plurality of memory cells and a bit line, the writing control method comprising:
generating an enable signal;
generating a control signal according to a characteristic value related to the number of the memory cells;
generating a voltage difference according to the enable signal and the control signal; and
applying the voltage difference to the bit line to cause a voltage drop on the bit line.

19. The writing control method of claim 18 further comprising:
applying a voltage to the memory cells in order that the memory cells have a voltage level by which the memory cells retain data stored therein;
wherein the step of generating the control signal according to the characteristic value related to the number of the memory cells comprises:
stopping applying the voltage to the memory cells according to the enable signal; and
decreasing the voltage level of the memory cells according to the enable signal and generating the control signal according to a change in the voltage level.

20. The writing control method of claim 18 , wherein a magnitude of the voltage drop is directly proportional to the number of the memory cells.

Assignees

• M31 Tech Corp

Inventors

• Lien Nan-Chun
• Yu David C

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title