Reducing registration and design vicinity induced noise for intra-die inspection

Patent metadata

Field	Value
Publication number	US-10074167-B2
Application number	US-201615355509-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Dec 6, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Noise induced by pattern-of-interest (POI) image registration and POI vicinity design patterns in intra-die inspection is reduced. POI are grouped into alignment groups by co-occurrence of proximate registration targets. The alignment groups are registered using the co-occurrence of proximate registration targets. Registration by voting is performed, which can measure a degree that each of the patterns-of-interest is an outlier. POI are grouped into at least one vicinity group with same vicinity design effects.

First claim

What is claimed is:

1. A system comprising:
a controller including a processor, an electronic data storage unit in electronic communication with the processor, and a communication port in electronic communication with the processor and the electronic data storage unit, wherein the controller is configured to:
group patterns-of-interest by co-occurrence of proximate registration targets into one or more alignment groups using an alignment target finder module;
register each alignment group using the co-occurrence of proximate registration targets offset by a same amount from the patterns-of-interest;
register by voting, wherein the registering by voting includes measuring a degree that each of the patterns-of-interest is an outlier; and
group the patterns-of-interest into at least one vicinity group with same vicinity design effects;

wherein the controller is in electronic communication with a review tool configured to generate a wafer image, wherein the review tool includes:
a stage configured to hold a wafer; and
an image generation system configured to generate the wafer image, wherein the image generation system is configured to use at least one of an electron beam, a broad band plasma, or a laser to generate the image of the wafer.

2. The system of claim 1 , wherein the controller is in electronic communication with a design based binning server.

3. The system of claim 1 , wherein the review tool is a scanning electron microscope.

4. The system of claim 1 , wherein at least some of the patterns-of-interest are in a rendered image that is based on a design file.

5. The system of claim 1 , wherein at least some of the patterns-of-interest are in the wafer image.

6. The system of claim 5 , wherein the wafer image is a scanning electron microscope image.

7. The system of claim 1 , wherein the controller is further configured to perform intelligent sampling with a sampling module prior to the grouping into the one or more alignment groups.

8. The system of claim 1 , wherein the controller is configured to perform intra-die inspection.

9. A method comprising:
receiving, at a controller, a wafer image from a review tool, wherein the review tool is configured to use at least one of an electron beam, a broad band plasma, or a laser to generate the wafer image of a wafer on a stage configured to hold the wafer;
grouping, using the controller, patterns-of-interest by co-occurrence of proximate registration targets into one or more alignment groups using an alignment target finder module, wherein at least some of the patterns-of-interest are in the wafer image;
registering, using the controller, each alignment group using the co-occurrence of proximate registration targets offset by a same amount from the patterns-of-interest;
registering by voting using the controller, wherein the registering by voting includes measuring a degree that each of the patterns-of-interest is an outlier; and
grouping, using the controller, the patterns-of-interest into at least one vicinity group with same vicinity design effects.

10. The method of claim 9 , wherein the grouping patterns-of-interest with same vicinity design effects occurs before the registration by voting, and wherein the registration by voting is performed on each of the at least one vicinity group.

11. The method of claim 9 , wherein the grouping patterns-of-interest with same vicinity design effects occurs after the registration by voting.

12. The method of claim 9 , wherein at least some of the patterns-of-interest are in a rendered image that is based on a design file.

13. The method of claim 9 , wherein the wafer image is a scanning electron microscope image.

14. The method of claim 9 , further comprising intelligent sampling with a sampling module prior to the grouping into the one or more alignment groups.

15. The method of claim 9 , wherein the co-occurrence of proximate registration targets in each of the alignment groups is offset by a same amount from the pattern-of-interest.

16. The method of claim 9 , wherein the registering by voting is configured to use information from a whole image population by taking a robust mean image as a registration template.

17. The method of claim 9 , wherein the registration by voting is configured to use information from a percentage of outliers in each of the alignment groups.

18. The method of claim 9 , wherein the method is for intra-die inspection.

Assignees

• Kla Tencor Corp

Inventors

• Banerjee Saibal
• Kulkarni Ashok
• Lu Shaoyu

Classifications

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G06T2207/10061

  from scanning electron microscope · CPC title

• G06T7/337

  involving reference images or patches · CPC title

• G06T7/0004 Primary

  Industrial image inspection · CPC title

• G06T7/0081

  Physics · mapped topic