Display controller and a method thereof

Patent metadata

Field	Value
Publication number	US-10074154-B2
Application number	US-201514709680-A
Country	US
Kind code	B2
Filing date	May 12, 2015
Priority date	Dec 12, 2014
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. The processing unit activates layers in the output image for displaying an output image on the display. The channels correspond to associated layers. The buffer controller adds to the respective fixed memory capacity of a particular buffer associated to an activated layer, one further fixed memory capacity of at least one further buffer associated to an inactive layer.

First claim

The invention claimed is:

1. A display controller for controlling a display, comprising:
a plurality of channels for fetching data from a memory;
a plurality of buffers coupled to the plurality of channels for receiving the fetched data from the plurality of channels, each buffer having a respective fixed memory capacity for storing the fetched data;
a buffer controller coupled to the plurality of buffers and the plurality of channels for controlling the buffers and the channels, respectively; and
a processing unit coupled to the buffers for receiving the data from the buffers, to the display for outputting a control signal to the display based on the received data, and to the buffer controller for controlling the buffers and channels;
the processing unit being arranged to activate layers in an output image for displaying the output image on the display via the control signal, the channels corresponding to associated layers, wherein the layers in the output image are stacked on top of each other;
the buffer controller being arranged to reassign a first fixed memory capacity of a first buffer coupled to a first channel and currently assigned to an inactive layer to a second fixed memory capacity of a second buffer coupled to a second channel and assigned to an activated layer to add to the respective fixed memory capacity of the second buffer.

2. A display controller according to claim 1 , the buffer controller being arranged to monitor a first number of activatable layers of a particular output image, the inactive layer being one or more of the activatable layers.

3. A display controller according to claim 2 , the buffer controller being arranged to associate the first number of activatable layers to a first particular area of the particular output image.

4. A display controller according to claim 3 , the buffer controller being arranged to associate one or more second numbers of activatable layers to one or more second particular areas of the particular output image, the one or more second numbers of activatable layers being equal or lower than the first number of activatable layers.

5. A display controller according to claim 3 , the processing unit further comprising a plurality of programmable registers for storing, for each activatable layer,
a corresponding address associated to the respective channel for reading the data from the memory,
a data format,
a size of the respective activatable layer,
a position of the respective activatable layer,
the programmable register having an output coupled to the buffer controller for outputting to the buffer controller the corresponding address, the data format, the size and the position of the respective activatable layer.

6. A display controller according to claim 5 , the programmable register further storing a parameter of the particular area, the parameter being one or more of the group consisting of: a location in the display, a width, a height, a size of the particular area.

7. A display controller according to claim 1 , the buffers being first-in first-out buffers.

8. A display system, comprising:
a display controller as claimed in claim 1 ,
a memory,
a system bus,
a central processing unit and
one or more further processing units,
the display controller, the central processing units and the one or more further processing units being coupled to the memory via the system bus for accessing data from the memory.

9. A system comprising the display system as claimed in claim 8 .

10. An automotive vehicle, comprising: a system as claimed in claim 8 , a display and a user interface coupled to the processing unit for outputting the output image on the display, the number of activatable layers based on the outputted image.

11. A method of controlling a display via a plurality of buffers, each buffer having a respective fixed memory capacity, the method comprising:
activating layers of an output image, the buffers being associated to the layers, wherein the layers in the output image are stacked on top of each other,
reassigning a first fixed memory capacity of a first buffer coupled to a first channel and currently assigned to an inactive layer to a second fixed memory capacity of a second buffer coupled to a second channel and assigned to an activated layer to add to the respective fixed memory capacity of the second buffer,
fetching data from a memory,
receiving the fetched data,
storing the fetched data into the plurality of buffers,
displaying the output image on the display via a control signal outputted to the display, the control signal based on the received data and the activated layers.

12. The method of claim 11 , the activating further comprising:
monitoring a first number of activatable layers of a particular image, the inactive layer being one or more of the activatable layers.

13. The method of claim 12 , the adding further comprising:
associating the first number of activatable layers to a first particular area of the particular output image.

14. The method of claim 13 , the adding further comprising:
associating one or more second numbers of activatable layers to one or more second particular areas of the particular output image, the one or more second numbers of activatable layers being equal or lower than the first number of activatable layers.

15. A computer program product comprising instructions for causing a programmable apparatus to perform a method of controlling a display as claimed in claim 11 .

16. A non-transitory tangible computer readable storage medium comprising data loadable in a programmable apparatus, the data representing instructions executable by the programmable apparatus, said instructions comprising:
one or more activate instructions for activating layers in an output image, a plurality of buffers being associating to the layers, each buffer having a fixed memory capacity, wherein the layers in the output image are stacked on top of each other,
one or more add instructions for reassigning a first fixed memory capacity of a first buffer coupled to a first channel and currently assigned to an inactive layer to a second fixed memory capacity of a second buffer coupled to a second channel and assigned to an activated layer to add to the respective fixed memory capacity of the second buffer,
one or more fetch instructions for fetching data from a memory,
one or more receive instructions for receiving the fetched data,
one or more store instructions for storing the fetched data in a plurality of buffers, each buffer having a respective fixed memory capacity, one or more display instructions for displaying the output image on the display via a control signal outputted to the display, the control signal being based on the received data and the activated layers.

Assignees

• Aubineau Vincent
• Depons Eric Eugene Bernard
• Staudenmaier Michael Andreas
• Nxp Usa Inc

Inventors

• Aubineau Vincent
• Depons Eric Eugene Bernard
• Staudenmaier Michael Andreas

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F5/065

  Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F2205/067

  Bidirectional FIFO, i.e. system allowing data transfer in two directions · CPC title