System, method and computer-accessible medium for fault analysis driven selection of logic gates to be camouflaged

Patent metadata

Field	Value
Publication number	US-10073728-B2
Application number	US-201414917456-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Sep 11, 2013
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.

First claim

What is claimed is:

1. A non-transitory computer-accessible medium including instructions thereon for camouflaging at least one logic gate in at least one integrated circuit, wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
determining at least one camouflaging location of the at least one logic gate using (i) a fault analysis procedure to model an incorrect reverse engineering configuration, and (ii) a fault simulation procedure to determine an effect of the incorrect reverse engineering configuration on at least one output of the at least one integrated circuit; and
camouflaging the at least one logic gate at the at least one location based on the determination.

2. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to perform the camouflaging procedure by replacing the at least one logic gate at the at least one camouflaging location with at least one further camouflaged gate which has at least one of at least one dummy contact or at least one vias.

3. The computer-accessible medium of claim 1 , wherein the at least one camouflaged gate is configured to corrupt a functionality of the at least one integrated circuit after being incorrectly reverse engineered as a logic gate type that is different from the at least one logic gate.

4. The computer-accessible medium of claim 3 , wherein the at least one logic gate is a plurality of logic gates, and wherein a number of the logic gates to be camouflaged is based on a number of outputs of the at least one integrated circuit that becomes corrupted during the reverse engineering.

5. The computer-accessible medium of claim 4 , wherein the number of corrupted outputs is about 50% of a total number of the outputs.

6. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to perform the camouflaging procedure using at least one interference graph.

7. The computer-accessible medium of claim 6 , wherein the computer arrangement is further configured to determine the at least one camouflaging location based on a clique analysis procedure performed on the interference graph.

8. The computer-accessible medium of claim 7 , wherein the computer arrangement is further configured to enhance an encryption of the at least one integrated circuit using at least one substantially maximally-sized clique of the clique analysis procedure.

9. The computer-accessible medium of claim 8 , wherein each of the at least one clique represents a set of non-resolvable and interfering camouflaged gates in a netlist.

10. The computer-accessible medium of claim 6 , wherein the at least one interference graph includes (i) at least one node related to the at least one camouflaging location, and (ii) at least one graph edge that is based on a degree of erasability of an effect of the at least one camouflaging location at least one of in or on at least one further camouflaging location.

11. The computer-accessible medium of claim 10 , wherein the at least one node represents a non-resolvable and interfering camouflaged gate.

12. The computer-accessible medium of claim 11 , wherein the at least one node is two nodes, and the nodes are connected by that at least one graph edge if the corresponding non-resolvable and interfering camouflaged gates protect each other.

13. The computer-accessible medium of claim 6 , wherein the computer arrangement is further configured to generate the at least one interference graph based at least in part on an effect of the plurality of camouflaging locations on at least one further camouflaging location of the at least one integrated circuit.

14. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured:
evaluate a plurality of camouflaging locations using the fault simulation procedure; and
select at least two of the camouflaging locations for placement of the at least one camouflaged logic gate.

15. The computer-accessible medium of claim 14 , wherein the selection of the camouflaging locations is performed using at least one of a Hamming Distance or Avalanche Criterion goals.

16. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the at least one camouflaging location based on an interference between two or more logic gates.

17. The computer-accessible medium of claim 16 , wherein the computer arrangement is further configured to determine the interference based on a first camouflaging location of a first logic gate of the two or more logic gates blocking a further camouflaging location of a further logic gate of the two or more logic gates.

18. The computer-accessible medium of claim 16 , wherein the computer arrangement is further configured to determine the interference based on a first output of a first logic gate of the two or more logic gates at a first camouflaging location and a second output of a second logic gate of the two or more logic gates at a second camouflaging location converging at a further camouflaging location of a further logic gate of the two or more logic gates.

19. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to watermark the at least one integrated circuit.

20. A method for camouflaging at least one logic gate in at least one integrated circuit comprising:
determining at least one camouflaging location of the at least one logic gate using (i) a fault analysis procedure to model an incorrect reverse engineering configuration, and (ii) a fault simulation procedure to determine an effect of the incorrect reverse engineering configuration on at least one output of the at least one integrated circuit; and
using a computer hardware arrangement, camouflaging the at least one logic gate in the at least one location based on the determination.

21. A system for camouflaging at least one logic gate in at least one integrated circuit comprising:
a computer hardware arrangement configured to:
determine at least one camouflaging location of the at least one logic gate using (i) a fault analysis procedure to model an incorrect reverse engineering configuration, and (ii) a fault simulation procedure to determine an effect of the incorrect reverse engineering configuration on at least one output of the at least one integrated circuit; and
camouflage the at least one logic gate in the at least one location based on the determination.

Assignees

• Univ New York

Inventors

• Rajendran Jeyavijayan
• Sinanoglu Ozgur
• Karri Ramesh

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0706

  the processing taking place on a specific hardware platform or in a specific software environment · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title