Self-assembled monolayer overlying a carbon nanotube substrate

Patent metadata

Field	Value
Publication number	US-10069093-B2
Application number	US-201715642066-A
Country	US
Kind code	B2
Filing date	Jul 5, 2017
Priority date	Nov 1, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a carbon nanotube substrate;
a self-assembled monolayer overlying the carbon nanotube substrate, the self-assembled monolayer providing a hydrophobic surface over the carbon nanotube substrate; and
a gate oxide overlying the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

2. The semiconductor device of claim 1 , wherein the tail group is chemically bonded to a surface of the carbon nanotube substrate to form the self-assembled monolayer.

3. The semiconductor device of claim 1 , wherein the self-assembled monolayer comprises molecules of a precursor that are applied to a surface of the carbon nanotube substrate, such that the molecules of the precursor are aligned substantially perpendicular with respect to the carbon nanotube substrate and substantially in parallel with respect to each other.

4. The semiconductor device of claim 1 , further comprising a tether material that tethers the self-assembled monolayer to the carbon nanotube substrate.

5. The semiconductor device of claim 1 , wherein the self-assembled monolayer is formed from a precursor comprising at least one of Undecanethiol (Thiol), Trichlorododecylsilane (DTS) and Triethoxy(octyl)silane (ODTS).

6. The semiconductor device of claim 1 , wherein semiconductor device is a Field Effect Transistor (FET).

7. The semiconductor device of claim 1 , wherein the carbon nanotube substrate further comprises at least one of chemical mechanical polished quartz, thermally oxidized silicon, and platinum.

8. A method, comprising:
forming a carbon nanotube substrate;
overlaying a precursor on a surface of the carbon nanotube substrate to form a self-assembled monolayer, the self-assembled monolayer providing a hydrophobic surface over the carbon nanotube substrate; and
overlaying a gate oxide on the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

9. The method of claim 8 , wherein overlaying the precursor comprises overlaying the precursor to the carbon nanotube substrate via at least one of spin-on, vapor prime, immersion, and Atomic Layer Deposition (ALD).

10. The method of claim 8 , wherein forming the carbon nanotube substrate comprises forming the carbon nanotube substrates from at least one of chemical mechanical polished quartz, thermally oxidized silicon, and platinum.

11. The method of claim 8 , further comprising controlling a hold time to provide a time for alignment of molecules of the precursor to be substantially perpendicular with respect to the carbon nanotube substrate and substantially in parallel with respect to each other, to form the self-assembled monolayer.

12. The method of claim 8 , further comprising overlaying a tether material layer on the carbon nanotube substrate, wherein overlaying the precursor comprises overlaying the precursor on a surface of the tether material layer to form the self-assembled monolayer.

13. The method of claim 8 , wherein the precursor comprises at least one of Undecanethiol (Thiol), Trichlorododecylsilane (DTS) and Triethoxy(octyl)silane (ODTS).

14. The method of claim 8 , further comprising delivering the precursor to the carbon nanotube substrate under vacuum via control of a vapor pressure of the precursor and a pulse duration of the precursor.

15. A method, comprising:
applying a precursor to a surface of a carbon nanotube substrate;
controlling a hold time of the precursor to provide a time for the precursor to chemically bond to the carbon nanotube substrate and physically transform into a self-assembled monolayer overlying the carbon nanotube substrate, the self-assembled monolayer providing a hydrophobic surface over the carbon nanotube substrate; and
overlaying a gate oxide onto the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

16. The method of claim 15 , wherein the precursor is applied to the carbon nanotube substrate via at least one of spin-on, vapor prime, immersion, and Atomic Layer Deposition (ALD).

17. The method of claim 15 , wherein forming the carbon nanotube substrate comprises forming the carbon nanotube substrates from at least one of chemical mechanical polished quartz, thermally oxidized silicon, and platinum.

18. The method of claim 15 , wherein controlling the hold time comprises controlling the hold time to control an alignment of molecules of the precursor to be substantially perpendicular with respect to the carbon nanotube substrate and substantially in parallel with respect to each other, to form the self-assembled monolayer.

19. The method of claim 15 , further comprising overlaying a tether material layer on the carbon nanotube substrate, wherein overlaying the precursor comprises overlaying the precursor on a surface of the tether material layer to form the self-assembled monolayer.

20. The method of claim 15 , wherein the precursor comprises at least one of Undecanethiol (Thiol), Trichlorododecylsilane (DTS) and Triethoxy(octyl)silane (ODTS).

Assignees

• Kelliher James T
• Lilly Monica P
• Howell Robert S
• Miller Wayne Stephen
• Shea Patrick B
• Walker Matthew J
• Sweet William J
• Northrop Grumman Systems Corp

Inventors

• Kelliher James T
• Lilly Monica P
• Howell Robert S
• Miller Wayne Stephen
• Shea Patrick B
• Walker Matthew J
• Sweet William J

Classifications

• H01L51/0533 Primary

  Electricity · mapped topic

• H01L51/0566

  Electricity · mapped topic

• H01L51/0048

  Electricity · mapped topic

• H10K10/476 Primary

  comprising at least one organic layer and at least one inorganic layer · CPC title

• H10K10/488

  the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction · CPC title