Memory structure having a magnetic tunnel junction (MTJ) self-aligned to a T-shaped bottom electrode, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10069064-B1
Application number	US-201715653180-A
Country	US
Kind code	B1
Filing date	Jul 18, 2017
Priority date	Jul 18, 2017
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A process flow for forming a magnetic tunnel junction (MTJ) cell that is self-aligned to an underlying bottom electrode (BE) is disclosed. The BE is comprised of a lower BE layer having a first width (w1), and an upper (second) BE layer with a second width (w2) where w2>w1. Preferably, the BE has a T shape. A stack of MTJ layers including an uppermost hard mask is deposited on the BE and has width w2 because of a self-aligned deposition process. A dummy MTJ stack is also formed around the first BE layer. An ion beam etch where ions are at an incident angle <90° with respect to the substrate is used to remove extraneous material on the sidewall. Thereafter, an encapsulation layer is deposited to insulate the MTJ cell, and to fill a gap between the first BE layer and dummy MTJ stack.

First claim

We claim:

1. A memory structure, comprising:
(a) a bottom electrode (BE) comprised of a first BE layer contacting a substrate, and a second BE layer adjoining a top surface of the first BE layer wherein the BE is substantially in the form of a T shape in which the first BE layer has a sidewall, and a top surface having a first width substantially less than a second width of the second BE layer, and the second BE layer has a second sidewall aligned essentially orthogonal with regard to the substrate; and
(b) a magnetic tunnel junction (MTJ) stack of layers formed on a top surface of the second BE layer, and having the second width and a sidewall that is coplanar with the second BE sidewall, wherein the MTJ stack is self-aligned to the bottom electrode.

2. The memory structure of claim 1 wherein the MTJ stack is a MTJ cell that has a bottommost seed layer on the second BE layer, a tunnel barrier layer formed between a pinned layer and a free layer, and an uppermost hard mask.

3. The memory structure of claim 1 wherein the second BE layer serves as a seed layer for the MTJ stack that includes a tunnel barrier layer formed between a free layer and a pinned layer, and an uppermost hard mask, and together with the MTJ stack forms a MTJ cell.

4. The memory structure of claim 1 further comprised of a dummy MTJ stack of layers that is electrically isolated from the MTJ stack of layers and BE, and formed on a top surface of the substrate, and surrounding the first BE layer such that a sidewall of the dummy MTJ stack is separated from the first BE sidewall by a gap.

5. The memory structure of claim 4 wherein the memory structure is further comprised of an encapsulation layer that insulates the MTJ stack from adjacent MTJ stacks of layers, and wherein the encapsulation layer fills the gap between the dummy MTJ stack of layers and first BE layer.

6. The memory structure of claim 4 wherein the first BE layer is comprised of Ta, TaN, Ti, or TiN, and has a first thickness greater than a thickness of the dummy stack of layers.

7. The memory structure of claim 6 wherein the second BE layer is comprised of Ni, NiCr, Ru, or NiFeCr, and has a second thickness less than the first thickness.

8. A memory structure, comprising:
(a) a bottom electrode (BE) comprised of a first BE layer contacting a substrate, and an upper second BE layer adjoining a top surface of the first BE layer wherein the BE is substantially in the form of a T shape in which the first BE layer has a sidewall, and a top surface having a first width substantially less than a second width of the second BE layer, and the second BE layer has a second sidewall aligned essentially orthogonal with regard to the substrate;
(b) a dielectric layer that is conformally formed on the second BE sidewall and a bottom surface of the second BE layer, and on the first BE layer sidewall and having a third sidewall proximate to the second BE sidewall that is aligned orthogonal with respect to the substrate; and
(c) a magnetic tunnel junction (MTJ) stack of layers that is self-aligned to the second BE layer and dielectric layer such that a sidewall on the MTJ stack is coplanar with the third sidewall, and the width of each of the MTJ stack of layers is greater than the second width.

9. The memory structure of claim 8 wherein the MTJ stack is a MTJ cell that has a bottommost seed layer on the second BE layer, a tunnel barrier layer formed between a pinned layer and a free layer, and an uppermost hard mask.

10. The memory structure of claim 8 wherein the second BE layer serves as a seed layer for the MTJ stack that includes a tunnel barrier layer formed between a free layer and a pinned layer, and an uppermost hard mask, and together with the MTJ stack forms a MTJ cell.

11. The memory structure of claim 8 further comprised of a dummy MTJ stack of layers that is electrically isolated from the MTJ stack of layers and BE, and formed on a top surface of the substrate, and surrounding the first BE layer such that a sidewall of the dummy MTJ stack is separated from the first BE sidewall by a gap.

12. The memory structure of claim 11 wherein the memory structure is further comprised of an encapsulation layer that insulates the MTJ stack of layers from adjacent MTJ stacks of layers, and wherein the encapsulation layer fills the gap between the dummy MTJ stack and first BE layer.

13. The memory structure of claim 11 wherein the first BE layer is comprised of Ta, TaN, Ti, or TiN, and has a first thickness greater than a thickness of the dummy MTJ stack of layers.

14. The memory structure of claim 13 wherein the second BE layer is comprised of Ni, NiCr, Ru, or NiFeCr, and has a second thickness less than the first thickness.

15. A method of forming a magnetic tunnel junction (MTJ) cell, comprising:
(a) forming a patterned bottom electrode (BE) wherein the BE has a first BE layer contacting a top surface of a substrate and having a first width (w 1 ) and a first sidewall, and a second BE layer with a second width (w 2 ) formed on a top surface of the first BE layer where w 2 >w 1 , and having a second sidewall aligned essentially orthogonal with respect to the substrate thereby forming a substantially T shape for the patterned bottom electrode;
(b) sputter depositing a MTJ stack of layers that is self-aligned to the second BE layer such that the MTJ stack has the second width and a sidewall that is coplanar with the second sidewall of the second BE layer; and
(c) cleaning the MTJ sidewall by performing an ion beam etch comprised of ions with an incident angle less than 90° with respect to the MTJ sidewall, and rotating the substrate.

16. The method of claim 15 wherein forming the patterned BE comprises:
(a) sequentially depositing the first BE layer, second BE layer, and a hard mask on the substrate;
(b) forming a photo mask on the hard mask, and then performing a first etch process to form a hard mask sidewall that stops on a top surface of the second BE layer;
(c) performing a second etch step to form the second BE sidewall that stops on the top surface of the first BE layer; and
(d) performing a third etch that is an isotropic process to selectively remove portions of the first BE layer thereby exposing the top surface of the substrate and forming the first BE sidewall having the first width.

17. The method of claim 16 wherein the second etch step is a reactive ion etch comprising a noble gas, MeOH, and a RF power that generates a plasma.

18. The method of claim 16 wherein the first BE layer is comprised of Ta, TaN, Ti, or TiN, and the second BE layer is comprised of Ni, NiCr, Ru, or NiFeCr.

19. The method of claim 15 wherein the second BE layer is a seed layer and together with the MTJ stack of layers forms a MTJ cell.

20. A method of forming a magnetic tunnel junction (MTJ) cell, comprising:
(a) forming a patterned bottom electrode (BE) wherein the BE has a first BE layer contacting a top surface of a substrate and having a first width (w 1 ) and a first sidewall, and a second BE layer with a second width (w 2 ) formed on a top surface of the first BE layer where w 2 >w 1 , and having a second sidewall aligned essentially orthogonal with respect to the substrate;
(b) forming a conformal dielectric layer on the first and second sidewalls and having a third sidewall proximate to the second sidewall wherein the third sidewall is aligned orthogonal with respect to the substrate;
(c) sputter depositing a MTJ stack of layers on the second BE layer, wherein the MTJ stack is self-aligned t

Assignees

• Headway Tech Inc

Inventors

• Haq Jesmin
• Zhong Tom
• Teng Zhongjian

Classifications

• H01L43/02 Primary

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title