Semiconductor device providing enhanced fin isolation and related methods

Patent metadata

Field	Value
Publication number	US-2015115370-A1
Application number	US-201314068340-A
Country	US
Kind code	A1
Filing date	Oct 31, 2013
Priority date	Oct 31, 2013
Publication date	Apr 30, 2015
Grant date	—

Abstract

A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

First claim

That which is claimed is:

1 . A method for making a semiconductor device comprising:
forming a first semiconductor layer on a substrate comprising a first semiconductor material; forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material; forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate; forming an oxide layer laterally surrounding the pillars and mask regions; removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar; etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar; and removing the inner spacers and forming an oxide beneath each semiconductor fin.

2 . The method of claim 1 wherein the first semiconductor material is selectively etchable with respect to the second semiconductor material.

3 . The method of claim 1 further comprising removing laterally adjacent portions of the oxide layer to expose the semiconductor fins.

4 . The method of claim 1 further comprising laterally etching perimeter portions of the first semiconductor layer of each pillar prior to forming the oxide layer.

5 . The method of claim 1 wherein etching comprises etching through at least some of the first semiconductor layer.

6 . The method of claim 1 wherein etching comprises etching through the first semiconductor layer and into the substrate.

7 . The method of claim 1 wherein etching comprises etching away all of the first semiconductor layer of each pillar.

8 . The method of claim 1 wherein the first semiconductor material comprises silicon germanium, and the second semiconductor material comprises silicon.

9 . The method of claim 1 further comprising forming a gate overlying the semiconductor fins.

10 . The method of claim 1 wherein the substrate comprises silicon.

11 . A semiconductor device comprising:
a substrate; an oxide layer on said substrate; at least one pair of semiconductor fins on said oxide layer, each fin comprising a first semiconductor material; and a semiconductor region within said oxide layer and between said at least one pair of semiconductor fins comprising a second semiconductor material different than the first material.

12 . The semiconductor device of claim 11 wherein said semiconductor region has a lateral width less than an inner distance between said at least one pair of semiconductor fins.

13 . The semiconductor device of claim 11 wherein said oxide layer comprises a respective vertical extension portion beneath each of said semiconductor fins.

14 . The semiconductor device of claim 11 wherein the first semiconductor material comprises silicon germanium, and the second semiconductor material comprises silicon.

15 . The semiconductor device of claim 11 further comprising forming a gate overlying the semiconductor fins.

16 . A semiconductor device comprising:
a substrate; an oxide layer on said substrate; and at least one pair of semiconductor fins on said oxide layer each comprising a first semiconductor material; wherein said substrate has a recess therein between said at least one pair of semiconductor fins, and wherein said oxide layer fills the recess.

17 . The semiconductor device of claim 16 wherein the recess has a lateral width less than an inner distance between said at least one pair of semiconductor fins.

18 . The semiconductor device of claim 16 wherein said oxide layer comprises a respective vertical extension portion beneath each of said semiconductor fins.

19 . The semiconductor device of claim 16 wherein the first semiconductor material comprises silicon germanium, and the second semiconductor material comprises silicon.

20 . The semiconductor device of claim 16 further comprising forming a gate overlying the semiconductor fins.

Assignees

• Globalfoundries Inc
• St Microelectronics Inc

Inventors

• Liu Qing
• Xie Ruilong
• Cho Hyun-Jin

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title