Reduction of parasitic capacitance in a semiconductor device

Patent metadata

Field	Value
Publication number	US-9123807-B2
Application number	US-201113019695-A
Country	US
Kind code	B2
Filing date	Feb 2, 2011
Priority date	Dec 28, 2010
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first region forming a source region;
a second region forming a drain region;
a third region forming a gate region between the source region and the drain region, the gate region having a first vertical side and a second vertical side and including a doped region and an undoped region, the doped region extending from the first vertical side of the gate region to a third vertical side and the undoped region extending from the third vertical side to the second vertical side of the gate region;
a silicide region formed onto the gate region, the silicide region not contacting at least a portion of a top side of the undoped region;
a first well region extending from a fourth vertical side to a fifth vertical side;
a second well region extending from a sixth vertical side to a seventh vertical side, at least a portion of the fifth vertical side of the first well region contacting at least a portion of the sixth vertical side of the second well region beneath the undoped region;
a first spacer formed between the first region and the gate region, the first spacer contacting at least a portion of the first vertical side of the gate region; and
a second spacer formed between the second region and the gate region, the second spacer contacting at least a portion of the second vertical side of the gate region.

2. The semiconductor device of claim 1 , wherein the doped region represents a first region within the gate region that is implanted with a dopant and the undoped region represents a second region within the gate region that is not implanted with the dopant.

3. The semiconductor device of claim 2 , wherein the dopant is an n-type material.

4. The semiconductor device of claim 2 , wherein the dopant is a p-type material.

5. The semiconductor device of claim 2 , wherein the doped region is heavily implanted with the dopant.

6. The semiconductor device of claim 2 , wherein the doped region is lightly implanted with the dopant.

7. The semiconductor device of claim 1 , wherein the doped region is characterized as having a first length and the undoped region is characterized as having a second length.

8. The semiconductor device of claim 7 , wherein the first length is less than the second length.

9. The semiconductor device of claim 7 , wherein the first length is approximately equal to the second length.

10. The semiconductor device of claim 1 , wherein the third vertical side represents a transition between the doped region and the undoped region.

11. The semiconductor device of claim 1 , wherein the source region and the drain region are implanted with an n-type material.

12. The semiconductor device of claim 1 , wherein the source region and the drain region are implanted with a p-type material.

13. The semiconductor device of claim 1 , wherein the silicide region is characterized as having a first length that is greater than a length of the doped region; and further comprising:
a second silicide region formed onto the drain region and displaced from the gate region by a second length.

14. The semiconductor device of claim 13 , wherein the second silicide region extends beyond the drain region toward the gate region.

15. The semiconductor device of claim 1 , wherein the first well region extends from the source region to the second well region; and
wherein the second well region extends from the drain region to the first well region.

16. The semiconductor device of claim 1 , wherein the first and the second well regions are p-type and n-type regions, respectively.

17. The semiconductor device of claim 1 , wherein the fifth vertical side of the first well region contacts at least a portion of the sixth vertical side of the second well region beneath the silicide region.

18. The semiconductor device of claim 1 , wherein the first and second spacers contact at least a portion of the first and second well regions, respectively.

19. A semiconductor device, comprising:
a source region;
a drain region;
a gate region formed between the source region and the drain region, the gate region having a first vertical side and a second vertical side and including a doped region and an undoped region, the doped region extending from the first vertical side of the gate region to a third vertical side and the undoped region extending from the third vertical side to the second vertical side of the gate region;
a first well region extending from a fourth vertical side to a fifth vertical side;
a second well region extending from a sixth vertical side to a seventh vertical side, at least a portion of the fifth vertical side of the first well region contacting at least a portion of the sixth vertical side of the second well region beneath the undoped region;
a first spacer formed between the source region and the gate region, the first spacer contacting at least a portion of the first vertical side of the gate region; and
a second spacer formed between the drain region and the gate region, the second spacer contacting at least a portion of the second vertical side of the gate region.

20. The semiconductor device of claim 19 , wherein the doped region represents a first region within the gate region that is implanted with a dopant and the undoped region represents a second region within the gate region that is not implanted with the dopant.

21. The semiconductor device of claim 20 , wherein the dopant is an n-type material.

22. The semiconductor device of claim 20 , wherein the dopant is a p-type material.

23. The semiconductor device of claim 19 , wherein the doped region is characterized as having a first length and the undoped region is characterized as having a second length.

24. The semiconductor device of claim 23 , wherein the first length is less than the second length.

25. The semiconductor device of claim 23 , wherein the first length is approximately equal to the second length.

26. The semiconductor device of claim 19 , wherein the third vertical side represents a transition between the doped region and the undoped region.

27. The semiconductor device of claim 19 , wherein the first well region extends from the source region to the second well region; and
wherein the second well region extends from the drain region to the first well region.

28. The semiconductor device of claim 19 , wherein the first and second well regions are p-type and n-type regions, respectively.

29. The semiconductor device of claim 19 , wherein the first and second spacers contact at least a portion of the first and second well regions, respectively.

Assignees

• Ito Akira
• Broadcom Corp

Inventors

• Ito Akira

Classifications

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/307

  the doping variations being parallel to the channel lengths · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D30/603 Primary

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title