Single-layer wiring package substrate, single-layer wiring package structure having the package substrate, and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10068842-B2
Application number	US-201715648089-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Dec 4, 2014
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

First claim

What is claimed is:

1. A method of fabricating a single-layer wiring package substrate, comprising:
forming a wiring layer having opposing first and second surfaces on a carrier, wherein the second surface of the wiring layer is in contact with the carrier;
forming a dielectric body on the carrier, wherein the dielectric body has a first side and a second side opposing the first side, and the second side of the dielectric body and the second surface of the wiring layer are disposed at a same side;
forming a first opening on the first side of the dielectric body with a portion of the wiring layer exposed from the first opening; and
removing the carrier with the second side of the dielectric body and the second surface of the wiring layer exposed.

2. The method of claim 1 , further comprising forming a second opening at the portion of the wiring layer exposed from the first opening, wherein the second opening corresponds in position to the first opening.

3. The method of claim 1 , wherein the dielectric body is made of a photosensitive dielectric material.

4. The method of claim 3 , wherein the first opening of the dielectric body is formed by an exposure and development process.

5. The method of claim 1 , wherein the second side of the dielectric body is coplanar with the second surface of the wiring layer.

6. The method of claim 1 , further comprising forming a seed layer on the carrier.

7. The method of claim 6 , further comprising:
removing the seed layer by an etching process; and
forming a second opening corresponding in position to the first opening by etching the first surface of the wiring layer.

8. A method of fabricating a package structure, comprising:
providing a dielectric body having a first side with a first opening and a second side opposing the first side, a single wiring layer being embedded in the dielectric body and having a first surface and a second surface opposing the first surface, wherein the second side of the dielectric body and the second surface of the single wiring layer are disposed at a same side, and a portion of the single wiring layer is exposed from the first opening;
forming on the first surface of the single wiring layer a second opening, wherein the second opening corresponds in position to the first opening; and
disposing on the second side of the dielectric body a semiconductor component electrically connected with the second surface of the single wiring layer.

9. The method of claim 8 , wherein the semiconductor component has a plurality of conductive bumps electrically connected with the second surface of the single wiring layer.

10. The method of claim 8 , further comprising forming on the dielectric body an encapsulant encapsulating the semiconductor component.

11. The method of claim 8 , further comprising filling an underfill between the semiconductor component and the second side of the dielectric body.

12. The method of claim 8 , wherein the dielectric body is made of a photosensitive dielectric material.

13. The method of claim 8 , wherein the second side of the dielectric body is coplanar with the second surface of the single wiring layer.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chiu Shih-Chao
• Lin Chun-Hsien
• Pai Yu-Cheng
• Hsiao Wei-Chung
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/073

  of die-attach connectors · CPC title