Systems and methods for adaptive error corrective code mechanisms

Patent metadata

Field	Value
Publication number	US-10067823-B2
Application number	US-201414560767-A
Country	US
Kind code	B2
Filing date	Dec 4, 2014
Priority date	Dec 4, 2014
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

Systems and methods for managing the endurance of a solid state drive by assigning error corrective codes (ECC) to a plurality of solid state drive blocks are provided. The disclosed systems and methods can provide a plurality of error corrective codes, each code having a corresponding correction capability and assign to each solid state drive block an error corrective code, according to a reliability of the solid state drive block. Moreover, the disclosed systems and methods can group the solid state drive blocks into groups according to their assigned error corrective codes and apply, for each group of solid state drive block, a level of ECC correction according to the assigned error corrective code of each group.

First claim

What is claimed is:

1. method for managing an endurance of a solid state drive, comprising:
providing a plurality of error corrective code (ECC) mechanisms, each mechanism having a corresponding correction capability;
assigning to each solid state drive block of a plurality of solid state drive blocks an error corrective code mechanism of the plurality of ECC mechanisms, according to a reliability of the solid state drive block;
monitoring the reliability of each solid state drive block based on a number of read-retry operations;
determining the number of read-retry operations associated with a first solid state drive block satisfies a threshold;
re-assigning to the first solid state block a different ECC mechanism of the plurality of ECC mechanisms based on the determination; and
applying, for the first solid state drive block, the different ECC mechanism for data operations in the first solid state drive block.

2. The method of claim 1 , wherein the different ECC mechanism is associated with a higher level of error correction than a previous ECC mechanism assigned to the first solid state drive block.

3. The method of claim 1 , wherein monitoring the reliability of the first solid state drive block is further based on at least one of a static rule and a dynamic rule.

4. The method of claim 3 , wherein the static rule includes at least one of a program-erase cycle of the first solid state drive block and read-retry operation information.

5. The method of claim 3 , wherein the dynamic rule includes at least one of a count of correctable errors, and a count of uncorrectable errors.

6. The method of claim 1 , further comprising determining that the reliability of the first solid state drive block has changed based on an uncorrectable error associated with the first solid state drive block.

7. The method of claim 6 , further comprising recovering data stored in the first solid state drive block.

8. The method of claim 7 , further comprising determining that the first solid state drive block is corrupted.

9. A memory controller comprising:
a controller module configured to:
communicate with a solid state drive having a plurality of blocks;
provide a plurality of error corrective code (ECC) mechanisms, each mechanism having a corresponding correction capability;
assign to each solid state drive block of the plurality of blocks an error corrective code mechanism of the plurality of ECC mechanisms, according to a reliability of the solid state drive block;
monitor the reliability of each solid state drive block based on a number of read-retry operations;
determine the number of read-retry operations associated with a first solid state drive block satisfies a threshold;
re-assign the first solid state drive block to a different ECC mechanism of the plurality of ECC mechanisms based on the determination; and
apply, for the first solid state drive block, the different ECC mechanism for data operations in the first solid state drive block.

10. The memory controller of claim 9 , wherein the different ECC mechanism is associated with a higher level of error correction than a previous ECC mechanism assigned to the first solid state drive block.

11. The memory controller of claim 9 , wherein monitoring the reliability of the first solid state drive block is further based on at least one of a static rule and a dynamic rule.

12. The memory controller of claim 11 , wherein the static rule includes at least one of a program-erase cycle of the first solid state drive block and read-retry operation information.

13. The memory controller of claim 11 , wherein the dynamic rule includes at least one of a count of correctable errors, and a count of uncorrectable errors.

14. The memory controller of claim 9 , wherein the controller module is further configured to determine that the reliability of the first solid state drive block has changed based on an uncorrectable error associated with the first solid state drive block.

15. The memory controller of claim 14 , wherein the controller module is further configured to recover data stored in the first solid state drive block.

16. The memory controller of claim 15 , wherein the controller module is further configured to determine that the first solid state drive block is corrupted.

Assignees

• HGST Netherlands BV
• Western Digital Tech Inc

Inventors

• Singhai Ashish
• Narasimha Ashwin
• Kumar Ajith

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title