Memory system changing a memory cell read voltage upon detecting a memory cell read error

Patent metadata

Field	Value
Publication number	US-9524786-B2
Application number	US-201414565522-A
Country	US
Kind code	B2
Filing date	Dec 10, 2014
Priority date	Nov 6, 2009
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile semiconductor memory device including a memory cell array having a plurality of blocks each including a plurality of memory cells; and
a control unit configured to set a voltage supplied to the memory cell in a read,
wherein
the control unit configured to set a first voltage supplied to the memory cell in a first read,
in a case that an error is detected after the first read, the control unit configured to set a second voltage supplied to the memory cell in a second read, the second voltage different from the first voltage,
in a case that an error is not detected after the second read, the control unit configured to record a data related to the second voltage.

2. The memory system according to claim 1 , wherein the second voltage is higher or lower than the first voltage.

3. The memory system according to claim 1 , wherein a time of the first read is different from a time of the second read.

4. The memory system according to claim 3 , wherein the time of the first read is different from the time of the second read by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense.

5. The memory system according to claim 3 , wherein a third voltage supplied to an unselected word line adjacent to a selected word line in the second read is higher than a forth voltage supplied to the unselected word line in the first read.

6. The memory system of claim 1 , wherein in a case that an error is detected after the second read, the control unit configured to set a fifth voltage supplied to the memory cell in a third read, the fifth voltage different from the first voltage and the second voltage,
in a case that an error is not detected after the third read, the control unit configured to record a data related to the fifth voltage.

7. The memory system of claim 6 , wherein the second voltage is higher than the first voltage and the fifth voltage is lower than the first voltage.

8. The memory system of claim 1 , wherein the control unit configured to set the second voltage supplied to the memory cell based on the data related to the second voltage in a fourth read after the second read.

9. The memory system of claim 8 , wherein in a case that an error is detected after the fourth read, the control unit configured to set the first voltage supplied to the memory cell in a fifth read.

Assignees

• Toshiba Kk

Inventors

• Nagashima Hiroyuki

Classifications

• G06F2201/88

  Monitoring involving counting · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title