Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment

Patent metadata

Field	Value
Publication number	US-10067187-B2
Application number	US-201414335720-A
Country	US
Kind code	B2
Filing date	Jul 18, 2014
Priority date	Jul 19, 2013
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. The test circuit includes multiple mask banks. Different mask patterns are stored in each of the mask banks. A first mask bank of the multiple mask banks is selected and the mask pattern stored in the selected first mask bank is used for masking the output of the scan chains of the test circuit during a first portion of a test cycle. A second mask bank of the multiple mask banks is selected and the ask pattern stored in the selected second mask bank is used for masking the output of the scan chains of the test circuit during a second portion of the test cycle.

First claim

What is claimed is:

1. A method for masking scan chains in a test circuit of an integrated circuit, comprising:
storing a plurality of mask patterns in the test circuit, each of the mask patterns stored in each of a plurality of mask banks in the test circuit;
initializing a counter;
controlling a multiplexer to couple an output of a first bank storing a first mask pattern to an input of a compressor of the test circuit;
masking an output of the scan chains of the test circuit in a test cycle by using the first mask pattern selected among the plurality of mask patterns;
updating the counter; and
responsive to the counter reaching a set value:
controlling the multiplexer to couple an output a second bank storing a second mask pattern to the input of the compressor of the test circuit, and
masking the output of the scan chains of the test circuit in a same test cycle by using the second mask pattern selected among the plurality of mask patterns.

2. The method of claim 1 :
wherein the first mask pattern is used at the beginning of the test cycle and the second mask pattern is used before an end of the test cycle; and
wherein the first mask pattern is further used after the using the second mask pattern and before the end of the test cycle.

3. The method of claim 2 , wherein the mask patterns are used in a round-robin manner.

4. The method of claim 1 , further comprising receiving control bits from a test input pin of the integrated circuit, the control bits including a mask bank selection bit indicating selection of one of the mask patterns to mask the output of the scan chains.

5. The method of claim 4 , wherein the control bits further comprises interval length control bits indicating a number of clock cycles during which the first or the second mask pattern is used, and further comprising:
setting a counter by the interval length control bits to generate a signal indicating switching from the first mask pattern to the second mask pattern.

6. The method of claim 1 , storing the plurality of mask patterns comprises:
receiving a first test pattern including the first mask pattern during the test cycle;
storing the first mask pattern in a first mask bank of test circuit responsive to receiving the first test pattern;
receiving a second test pattern including the second mask pattern during another test cycle; and
storing the second mask pattern in a second mask bank of the test circuit responsive to receiving the second test pattern.

7. A test circuit in an integrated circuit comprising:
a compressor coupled to receive and compress scan outputs from scan chains;
a counter;
a plurality of mask banks, each of the mask banks configured to store a mask pattern; and
a multiplexer between the compressor and the mask banks, the multiplexer configured to:
couple an output of a first mask bank storing a first mask pattern to an input of the compressor of the test circuit in response to the counter having a value lower than a set value,
couple an output a second mask bank storing a second mask pattern to the input of the compressor of the test circuit in response to the counter reaching the set value;

wherein the compressor is configured to:
mask an output of the scan chains of the test circuit in a test cycle by using the first mask pattern selected among the plurality of mask patterns in response the multiplexer coupling the output of the first mask bank to the input of the compressor, and
mask the output of the scan chains of the test circuit in a same test cycle by using the second mask pattern selected among the plurality of mask patterns in response to the multiplexer coupling the output of the second mask bank to the input of the compressor.

8. The test circuit of claim 7 , further comprising:
a counter coupled to the multiplexer and configured generate a counter signal indicative of the first period and the second period based on a clock signal; and
a bank selector coupled between the counter and the multiplexer, the bank selector configured to generate a select signal representing a selected mask bank responsive to receiving the counter signal.

9. The test circuit of claim 7 , further comprising a mask bank clock demultiplexer having a plurality of outputs, each output coupled to a clock input of a mask bank from the plurality of mask banks to select a mask bank for storing a mask pattern.

10. The test circuit of claim 9 , further comprising a register coupled to a test input pin of the integrated circuit to receive and store control bits, the control bits comprising a mask pattern and mask bank selection bits, the mask bank clock demultiplexer configured to select one mask bank of the plurality of mask banks to load the mask pattern into the selected mask bank.

11. The test circuit of claim 10 , wherein the control bits further comprise interval length bits specifying a modulo of the counter.

12. A non-transitory computer readable medium configured to store a design of a test circuit of an integrated circuit, the design of the test circuit comprising:
a compressor coupled to receive and compress scan outputs from scan chains;
a counter;
a plurality of mask banks, each of the mask banks configured to store a mask pattern; and
a multiplexer between the compressor and the mask banks, the multiplexer configured to:
couple an output of a first bank storing a first mask pattern to an input of a compressor of the test circuit in response to the counter having a value lower than a set value,
couple an output a second bank storing a second mask pattern to the input of the compressor of the test circuit in response to the counter reaching the set value;

wherein the compressor is configured to:
mask an output of the scan chains of the test circuit in a test cycle by using the first mask pattern selected among the plurality of mask patterns in response the multiplexer coupling the output of the first mask bank to the input of the compressor, and
mask the output of the scan chains of the test circuit in a same test cycle by using the second mask pattern selected among the plurality of mask patterns in response to the multiplexer coupling the output of the second mask bank to the input of the compressor.

13. The non-transitory computer readable medium of claim 12 wherein the first mask bank is selected at the beginning of a test cycle, and the second mask bank is selected before the end of the test cycle.

14. The non-transitory computer readable medium of claim 13 wherein the first mask bank is further selected during a third period, the third period being after the second period, and the third period being before the end of the test cycle.

15. The non-transitory computer readable medium of claim 13 wherein the mask banks are selected in a round-robin manner.

16. The non-transitory computer readable medium of claim 15 , wherein the design of the test circuit further comprises:
a counter coupled to the multiplexer and configured generate a counter signal indicative of the first period and the second period based on a clock signal; and
a bank selector coupled between the counter and the multiplexer, the bank selector configured to generate a select signal representing a selected mask bank responsive to receiving the counter signal.

17. The non-transitory computer readable medium of claim 15 wherein the design of the test circuit further comprises a mask bank clock demultiplexer having a plurality of outputs, each output coupled to a clock input of a mask bank from the plurality of mask banks to select a mask bank for storing a mask patter

Assignees

• Synopsys Inc

Inventors

• Chandra Anshuman
• Chebiyam Subramanian
• Saikia Jyotirmoy
• Bhattacharya Parthajit
• Kapur Rohit

Classifications

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/318547 Primary

  Data generators or compressors · CPC title