Leakage tolerant oscillator

Patent metadata

Field	Value
Publication number	US-10063188-B2
Application number	US-201615140717-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Apr 28, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.

First claim

What is claimed is:

1. A circuit comprising:
a first integrated circuit terminal;
a feedback network;
a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness, the first gate terminal being coupled to the first integrated circuit terminal and the feedback network, the thick gate native transistor having a first threshold voltage, the thick gate native transistor being configured as a source follower; and
a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness, the second gate terminal being coupled to a source terminal of the thick gate native transistor, the second transistor having a second threshold voltage, the second transistor having an amplifier configuration.

2. The circuit, as recited in claim 1 , wherein a first magnitude of the first threshold voltage is less than a second magnitude of the second threshold voltage.

3. The circuit, as recited in claim 1 , wherein the first threshold voltage has a magnitude of approximately zero volts.

4. The circuit, as recited in claim 1 , wherein a first gate leakage current of the thick gate native transistor is less than a second gate leakage current of the second transistor.

5. The circuit, as recited in claim 1 , wherein the second gate terminal is coupled to a low-impedance path to a bias node.

6. The circuit, as recited in claim 1 , further comprising:
a second integrated circuit terminal coupled to a drain terminal of the second transistor; and
an oscillator circuit comprising:
the feedback network, wherein the feedback network comprises:
a resistor coupled between the first integrated circuit terminal and the second integrated circuit terminal; and
a first capacitor coupled to the first integrated circuit terminal;

a second capacitor coupled to the second integrated circuit terminal; and
an amplifier circuit coupled between the first integrated circuit terminal and the second integrated circuit terminal, the amplifier circuit comprising the thick gate native transistor and the second transistor.

7. The circuit, as recited in claim 1 , further comprising:
a third transistor having a third gate terminal with a third gate thickness greater than the second gate thickness, the third transistor having a third threshold voltage, the third transistor being configured as a common source amplifier, the third gate terminal being coupled to the first integrated circuit terminal.

8. The circuit, as recited in claim 7 , wherein the first threshold voltage has a magnitude of approximately zero volts, the second threshold voltage has a magnitude greater than approximately zero volts, and the third threshold voltage has a magnitude greater than the second threshold voltage.

9. The circuit, as recited in claim 7 , further comprising:
a buffer comprising the third transistor, the buffer being configured to provide an oscillating signal to a circuit comprising additional transistors having the second threshold voltage and having corresponding gate terminals with the second gate thickness.

10. The circuit, as recited in claim 1 , further comprising:
a second integrated circuit terminal; and
an oscillator circuit comprising:
the feedback network, wherein the feedback network comprises:
a first capacitor coupled to the first integrated circuit terminal; and
a feedback resistor coupled between an output of an inverter circuit and the first gate terminal;

a second capacitor coupled to the second integrated circuit terminal;
a resistor coupled between the second integrated circuit terminal and a drain terminal of the second transistor; and
the inverter circuit, the inverter circuit being coupled to the resistor, the inverter circuit comprising the second transistor and an additional transistor of a second conductivity type having a third gate terminal coupled to the source terminal of the thick gate native transistor.

11. The circuit, as recited in claim 1 , further comprising:
an oscillator circuit comprising:
the thick gate native transistor and the second transistor;
the feedback network, wherein the feedback network comprises:
a resistor coupled to the first gate terminal and a first bias node; and
a first capacitor coupled to the first gate terminal of the thick gate native transistor and a source terminal of the second transistor; and

a second capacitor coupled to the source terminal of the second transistor and a second bias node.

12. A method comprising:
providing a signal, to a circuit including at least one transistor, based on a feedback signal and a first signal received from a first integrated circuit terminal, by a second circuit comprising a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness, the first gate terminal being coupled to the first integrated circuit terminal, the thick gate native transistor having a first threshold voltage, the thick gate native transistor being configured as a source follower, the at least one transistor having a second threshold voltage having a magnitude greater than a magnitude of the first threshold voltage, the at least one transistor being configured as an amplifier.

13. The method, as recited in claim 12 , wherein the providing comprises:
isolating a second transistor from the first integrated circuit terminal using the thick gate native transistor, the second transistor having a second gate terminal with a second gate thickness less than the first gate thickness, the second transistor having the second threshold voltage, and the second gate terminal being coupled to a source terminal of the thick gate native transistor.

14. The method, as recited in claim 13 , wherein a first magnitude of the first threshold voltage is less than a second magnitude of the second threshold voltage and a first gate leakage current of the thick gate native transistor is less than a second gate leakage current of the second transistor.

15. The method, as recited in claim 13 , wherein the second circuit is an oscillator circuit and the signal is a first oscillating signal, the method further comprising:
calibrating the second circuit based on at least one of a duty cycle of a second oscillating signal on the first integrated circuit terminal and a DC voltage level on the first integrated circuit terminal.

16. The method, as recited in claim 15 , wherein the calibrating comprises:
measuring at least one of the duty cycle of the second oscillating signal on the first integrated circuit terminal and the DC voltage level on the first integrated circuit terminal; and
adjusting a device parameter of at least one of the thick gate native transistor, the second transistor, and a third transistor based on the at least one of the duty cycle of the second oscillating signal on the first integrated circuit terminal and the DC voltage level on the first integrated circuit terminal.

17. The method, as recited in claim 13 , further comprising:
buffering the signal using at least a third transistor having a third gate terminal with a third gate thickness greater than the second gate thickness, the third transistor having a third threshold voltage, the third transistor being configured as a common source amplifier, the third gate terminal being coupled to the first integrated circuit terminal.

18. The method, as recited in claim 17 , wherein the first threshold voltage has a magnitude of approximately zero volts, the second threshold voltage has a ma

Assignees

• Silicon Lab Inc

Inventors

• Srinivas Shail

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H01L21/00

  Electricity · mapped topic

• H03K17/063

  in field-effect transistor switches · CPC title

• H03B5/36

  active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title