Package substrate

Patent metadata

Field	Value
Publication number	US-10062649-B2
Application number	US-201615386456-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Jan 15, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

This disclosure provides a package substrate which includes: a first conductive layer having a first conductive area and a second conductive area; a package unit layer disposed on the first conductive layer and including a first circuit device having a first terminal connected to the first conductive area and a second terminal connected to the second conductive area, a first conductive pillar connected to the first conductive area, and an encapsulant material; and a second conductive layer disposed on the package unit layer and having a first metal wire connected to the first conductive pillar.

First claim

What is claimed is:

1. A package substrate, comprising:
a first conductive layer, comprising:
a first planar conductive area; and
a second planar conductive area;

a package unit layer disposed on the first conductive layer, comprising:
a first circuit device, comprising:
a first terminal, connected to the first planar conductive area; and
a second terminal, connected to the second planar conductive area;

a first conductive pillar, neighboring the first circuit device and connected to the first planar conductive area; and
an encapsulant material, surrounding the first circuit device and the first conductive pillar; and

a second conductive layer, disposed on the package unit layer, comprising a first metal wire connected to the first conductive pillar.

2. The package substrate of claim 1 , wherein the first circuit device is a multi-layer ceramic capacitor.

3. The package substrate of claim 1 , wherein the package unit layer consists of the first circuit device, the first conductive pillar and the encapsulant material.

4. The package substrate of claim 1 , wherein the package unit layer further comprises a second conductive pillar connected to the second planar conductive area, and the second conductive layer further comprises a second metal wire connected to the second conductive pillar.

5. The package substrate of claim 1 , wherein the package unit layer further comprises a second circuit device having a third terminal connected to the first planar conductive area.

6. The package substrate of claim 1 , wherein the first conductive layer further comprises a third conductive area, and the package unit layer further comprises:
a second circuit device having a third terminal connected to the first planar conductive area and a fourth terminal connected to the third conductive area;
a second conductive pillar connected to the second planar conductive area; and
a third conductive pillar connected to the third conductive area.

7. The package substrate of claim 1 , wherein the package unit layer further comprises a connection unit, and the second conductive layer further comprises a second metal wire connected to the second terminal of the first circuit device through the connection unit.

8. The package substrate of claim 5 , wherein the package unit layer further comprises a first connection unit, a second connection unit and a third connection unit; and the second conductive layer further comprises a second metal wire connected to the second terminal of the first circuit device through the first connection unit, and a third metal wire connected to the first terminal of the first circuit device through the second connection unit; wherein the first metal wire is connected to the third terminal of the second circuit device through the third connection unit.

9. The package substrate of claim 1 , wherein said first terminal is directly connected to a first conductive pad, said first conductive pad is directly connected to said first planar conductive area, said second terminal is directly connected to a second conductive pad, and said second conductive pad is directly connected to said second planar conductive area.

10. The package substrate of claim 8 , wherein said first terminal is directly connected to a first conductive pad, said first conductive pad is directly connected to said first planar conductive area, said second terminal is directly connected to a second conductive pad, and said second conductive pad is directly connected to said second planar conductive area.

Assignees

• Phoenix Pioneer Technology Co Ltd
• Phoenix & Corp

Inventors

• Hsu Shih-Ping
• Yang Chih-Kuai

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title