Method and system for constructing FINFET devices having a super steep retrograde well

Patent metadata

Field	Value
Publication number	US-10062612-B2
Application number	US-201615288503-A
Country	US
Kind code	B2
Filing date	Oct 7, 2016
Priority date	Oct 7, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

First claim

What is claimed is:

1. A method for forming a finFET device, comprising:
forming a plurality of recesses in a semiconductor wafer to form a plurality of fins therebetween, a first portion of the recesses being relatively narrower than a second portion of the recesses;
forming a first layer of doped silicate glass above the semiconductor wafer and within the plurality of recesses;
forming a first layer of nitride above the first doped silicate glass layer;
forming a conformal oxide layer above the first nitride layer, substantially filling the first portion of relatively narrower recesses and lining the second portion of recesses;
removing the conformal oxide layer from a top surface of the plurality of the fins;
removing the first doped silicate glass layer, the first nitride layer, and the conformal oxide layer adjacent a first portion of the plurality of fins and recesses;
forming a second layer of doped silicate glass having an opposite doping polarity to the first doped silicate glass above the wafer;
removing the second layer of doped silicate glass layer and at least a portion of the conformal oxide layer from above the first doped silicate glass layer, wherein the removing comprises forming a second mask above at least a portion of the plurality of fins and recesses free from the first doped silicate glass layer; and removing the second doped silicate glass layer and the conformal oxide layer from the plurality of fins and recesses free of the second mask;
forming a second layer of nitride above the semiconductor wafer;
performing a shallow trench isolation process to at least partially fill the plurality of recesses; and
removing a portion of the material in the plurality of recesses to reveal the plurality of fins.

2. A method, as set forth in claim 1 , wherein removing the first doped silicate glass layer, the first nitride layer, and the conformal oxide layer adjacent the first portion of the plurality of fins and recesses further comprises:
forming a first mask over a second portion of the plurality of fins and recesses;
removing the first doped silicate glass layer, the first nitride layer, and the conformal oxide layer from the plurality of fins and recesses free of the first mask.

3. A method, as set forth in claim 1 , further comprising:
removing the first nitride layer from above the first doped silicate glass layer.

4. A method, as set forth in claim 1 , wherein forming the first layer of doped silicate glass above the semiconductor wafer and within the plurality of recesses further comprises forming the first layer of doped silicate glass having a thickness in the range of about 0.5 nm to about 6 nm.

5. A method, as set forth in claim 1 , wherein forming the first layer of nitride above the first doped silicate glass layer further comprises forming the first layer of nitride having a thickness in the range of about 1 nm to about 6 nm.

6. A method, as set forth in claim 1 , wherein forming the layer of conformal oxide above the first layer of nitride further comprises forming the first layer of conformal oxide having a thickness in the range of about 2 nm to about 15 nm.

7. A method, as set forth in claim 1 , wherein forming the second layer of doped silicate glass above the semiconductor wafer further comprises forming the second layer of doped silicate having a thickness in the range of about 0.5 nm to about 6 nm.

8. A method, as set forth in claim 1 , wherein forming the second layer of nitride above the semiconductor wafer further comprises forming the second layer of nitride having a thickness in the range of about 1 nm to about 6 nm.

9. A method, as set forth in claim 1 , wherein the first doped silicate glass layer is comprised of borosilicate glass (BSG), and the second doped silicate glass layer is comprised of phosphosilicate glass (PSG).

10. A method, as set forth in claim 1 , wherein the first doped silicate glass layer is comprised of phosphosilicate glass (PSG), and the second doped silicate glass layer is comprised of borosilicate glass (BSG).

11. A method for forming a finFET device, comprising:
forming a plurality of recesses in a semiconductor wafer to form a plurality of fins therebetween;
forming a first layer of doped silicate glass above the semiconductor wafer and within the plurality of recesses;
forming a first layer of nitride above the first doped silicate glass layer;
forming an oxide layer above the nitride layer, substantially filling a first portion of the plurality of recesses and forming a layer of oxide on sidewall and bottom surfaces of a second portion of the recesses;
removing the oxide layer from a top surface of the plurality of the fins and the bottom surface of the second portion of the recesses;
forming a first mask over a portion of the plurality of fins and recesses;
removing the first doped silicate glass layer, the nitride layer, and the oxide layer from the plurality of fins and recesses free of the first mask;
removing the first mask;
forming a second layer of doped silicate glass above the wafer;
forming a second mask above at least a portion of the plurality of fins and recesses free from the first doped silicate glass layer;
removing the second doped silicate glass layer and at least a portion of the oxide layer from the plurality of fins and recesses free of the second mask;
removing the second mask;
forming a second layer of nitride above the semiconductor wafer;
performing a shallow trench isolation process to at least partially fill the plurality of recesses; and
removing a portion of the material in the plurality of recesses to reveal the plurality of fins.

12. A method, as set forth in claim 11 , wherein forming the first doped silicate glass layer above the semiconductor wafer and within the plurality of recesses further comprises forming the first layer of doped silicate glass having a thickness in the range of about 0.5 nm to about 6 nm.

13. A method, as set forth in claim 11 , wherein forming the first layer of nitride above the first doped silicate glass layer further comprises forming the first layer of nitride having a thickness in the range of about 1 nm to about 6 nm.

14. A method, as set forth in claim 11 , wherein forming the layer of oxide above the first layer of nitride further comprises forming the first layer of nitride having a thickness in the range of about 2 nm to about 15 nm.

15. A method, as set forth in claim 11 , wherein forming the second layer of doped silicate glass above the semiconductor wafer further comprises forming the layer of PSG having a thickness in the range of about 0.5 nm to about 6 nm.

16. A method, as set forth in claim 11 , wherein forming the second layer of nitride above the semiconductor wafer further comprises forming the second layer of nitride having a thickness in the range of about 1 nm to about 6 nm.

17. A method, as set forth in claim 11 , wherein removing the second doped silicate glass layer and at least a portion of the oxide layer from the plurality of fins and recesses free of the second mask further comprises removing substantially all of the oxide layer from the plurality of fins and recesses free of the second mask.

18. A method, as set forth in claim 11 , wherein the first doped silicate glass layer is comprised of borosilicate glass (BSG), and the second doped silicate glass layer is comprised of phosphosilicate glass (PSG).

19. A method, as set forth in claim 11 , wherein the first doped silicate glass layer is comprised of phosphosilicate glass (PSG), and the second

Assignees

• Globalfoundries Inc

Inventors

• Brunco David Paul
• Jaeger Daniel

Classifications

• H10P14/6923

  the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG · CPC title

• H01L21/02129

  Electricity · mapped topic

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic