Methods of fabricating a semiconductor device having a via structure and an interconnection structure

Patent metadata

Field	Value
Publication number	US-10062606-B2
Application number	US-201715837132-A
Country	US
Kind code	B2
Filing date	Dec 11, 2017
Priority date	Dec 3, 2014
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, and forming a middle interlayer insulating layer covering the lower interlayer insulating layer and the conductive base structure. The methods include etching the middle interlayer insulating layer to form a via hole and an interconnection trench vertically aligned with the via hole, and forming a via barrier layer on inner walls of the via hole and an interconnection barrier layer on inner walls and a bottom of the interconnection trench, the via barrier layer not being formed on an upper surface of the conductive base structure The methods include forming a via plug on the via barrier layer to fill the via hole, forming a seed layer on the interconnection trench and the via plug, forming an interconnection electrode on the seed layer, and forming an interconnection capping layer on the interconnection electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lower interlayer insulating layer surrounding sidewalls of a conductive base structure;
a middle interlayer insulating layer on the lower interlayer insulating layer;
a via structure extending through the middle interlayer insulating layer and connected with the conductive base structure; and
an interconnection structure in the middle interlayer insulating layer, the interconnection structure being aligned with the via structure,
the via structure including,
a via barrier layer on inner walls of a via hole,
the via barrier layer not being formed on an upper surface of the conductive base structure, and
the via hole extending through the middle interlayer insulating layer to expose the upper surface of the conductive base structure, and

a via plug on the via barrier layer to fill the via hole,

the interconnection structure including,
an interconnection barrier layer on inner walls and a bottom of an interconnection trench, the interconnection trench being aligned with the via hole, and
an interconnection electrode on the interconnection barrier layer to fill the interconnection trench, and

the via barrier layer being materially in continuity with the interconnection barrier layer.

2. The semiconductor device of claim 1 , further comprising:
a seed layer between the interconnection barrier layer and the interconnection electrode,
the seed layer extending onto an upper surface of the via plug.

3. The semiconductor device of claim 2 , further comprising:
a liner layer between the seed layer and the interconnection barrier layer,
the liner layer extending onto the upper surface of the via plug.

4. The semiconductor device of claim 1 , wherein the interconnection structure further comprises an interconnection capping layer on an upper surface of the interconnection electrode.

5. The semiconductor device of claim 1 , wherein a bottom of the via plug and the upper surface of the conductive base structure are in contact with each other.

6. A semiconductor device, comprising:
a lower stopper layer and an interlayer insulating layer on a base structure;
a via structure extending through both the interlayer insulating layer and the lower stopper layer to be connected with the base structure; and
an interconnection structure in the interlayer insulating layer, the interconnection structure being aligned with the via structure,
the via structure including,
a via plug filling a via hole, the via hole extending through the interlayer insulating layer to expose an upper surface of the base structure, and

the interconnection structure including,
an interconnection barrier layer on inner walls and a bottom of an interconnection trench, the interconnection trench being aligned with the via hole,
a liner layer on the upper surfaces of the interconnection barrier layer and the via plug,
a seed layer on the liner layer, and
an interconnection electrode on the seed layer to fill the interconnection trench.

7. The semiconductor device of the claim 6 , wherein the interconnection barrier layer extends between the upper surface of the via plug and the liner layer.

8. The semiconductor device of claim 6 , wherein the liner layer is in direct contact with the upper surface of the via plug.

9. The semiconductor device of claim 6 , wherein
the via structure further comprises a via barrier layer surrounding sidewalls of the via plug, and
the via barrier layer is not formed on the upper surface of the base structure.

10. The semiconductor device of claim 6 , wherein the upper surface of the via plug is lower than the bottom of the interconnection trench.

11. The semiconductor device of claim 6 , wherein
the interconnection structure further comprises an interconnection capping layer on an upper surface of the interconnection electrode, and
the interconnection capping layer protrudes from the upper surface of the interlayer insulating layer.

12. The semiconductor device of claim 6 , wherein the base structure comprises:
a base electrode, and
a base barrier layer surrounding the base electrode.

13. The semiconductor device of claim 6 , wherein the liner layer comprises at least one selected from Co and Ru.

14. The semiconductor device of claim 6 , wherein the via plug comprises at least one selected from Co and Ru.

15. The semiconductor device of claim 6 , wherein
the via barrier layer and the interconnection barrier layer are single layers or multi-layers, and
the via barrier layer and the interconnection barrier layer include at least one selected from TaN, TiN, and Mn.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Siew Yongkong
• Park Seongho

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title