Devices, system, and methods for implementing alternate control settings

Patent metadata

Field	Value
Publication number	US-10062444-B2
Application number	US-201615018109-A
Country	US
Kind code	B2
Filing date	Feb 8, 2016
Priority date	Jun 18, 2012
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first set of storage cells configured to store a first set of control settings;
a second set of storage cells configured to store a second set of alternate control settings; and
a non-volatile control cell coupled to the first set of storage cells and to the second set of storage cells, the non-volatile control cell having a state to indicate whether to use the first set of control settings or the second set of alternate control settings to control one or more operating parameters of the integrated circuit.

2. The integrated circuit of claim 1 , wherein at least one of the first set of storage cells or the second set of storage cells comprise non-volatile storage cells.

3. The integrated circuit of claim 1 , wherein at least one of the first set of storage cells or the second set of storage cells comprise one-time programmable cells.

4. The integrated circuit of claim 1 , wherein at least one of the first set of storage cells or the second set of storage cells comprise fuse links or anti-fuse links.

5. The integrated circuit of claim 1 , further comprising a third set of storage cells to store an additional set of control settings, wherein the additional set of control settings control additional operating parameters of the integrated circuit.

6. The integrated circuit of claim 1 , further comprising:
a multiplexer coupled to an output of the non-volatile control cell, the multiplexer including;
a first set of inputs coupled to outputs of the first set of storage cells;
a second set of inputs coupled to outputs of the second set of storage cells;
wherein the state of the non-volatile control cell configures the multiplexer to use either the first set of inputs or the second set of inputs; and
a multiplexer output configured to control the one or more operating parameters of the integrated circuit based on either the first set of inputs or the second set of inputs.

7. The integrated circuit of claim 1 , further comprising:
an array of non-volatile memory cells including the first set of storage cells and the second set of storage cells; and
a control circuit coupled to the non-volatile control cell and configured to access the array based on the state of the non-volatile control cell, and to write values, based on information accessed from the array, into one or more registers, to control the one or more operating parameters of the integrated circuit.

8. The integrated circuit of claim 1 , further comprising:
an array of non-volatile memory cells including the first set of storage cells and the second set of storage cells; and
address lines coupled to the array to control which memory cells of the array are accessed;
wherein a state of the non-volatile control cell determines a state of the address lines.

9. A method to initialize an integrated circuit comprising:
loading, during an initialization phase, a register with a first value based on information stored in a first set of storage cells if a non-volatile control cell is in a first state; and
loading, during the initialization phase, the register with a second value based on information stored in a second set of storage cells if the non-volatile control cell is in a second state.

10. The method of claim 9 , wherein the initialization phase occurs while a reset line is asserted to the integrated circuit.

11. The method of claim 9 , wherein the initialization phase occurs in response to an application of power to the integrated circuit.

12. The method of claim 9 , further comprising:
loading, if the non-volatile control cell is in the second state, the register with the first value, before the loading of the register with the second value.

13. An electronic system comprising:
a processor configured to generate memory control commands;
a memory coupled to the processor; and
an input/output circuit coupled to the processor;
wherein at least one of the processor, the memory, or the input/output circuit comprise:
a first set of storage cells configured to store a first set of control settings;
a second set of storage cells configured to store a second set of alternate control settings; and
a non-volatile control cell coupled to the first set of storage cells and to the second set of storage cells, the non-volatile control cell having a state to indicate whether to use the first set of control settings or the second set of alternate control settings to control one or more operating parameters the electronic system.

14. The electronic system of claim 13 , wherein at least one of the first set of storage cells or the second set of storage cells comprise non-volatile cells.

15. The electronic system of claim 13 , wherein at least one of the first set of storage cells or the second set of storage cells comprise one-time programmable cells.

16. The electronic system of claim 13 , wherein at least one of the first set of storage cells or the second set of storage cells comprise fuse links or anti-fuse links.

17. The electronic system of claim 13 , wherein at least one of the processor, the memory, or the input/output circuit further comprise:
a third set of storage cells configured to store a third set of additional control settings;
wherein the third set of additional control settings control additional operating parameters of the electronic system.

18. The electronic system of claim 13 , wherein at least one of the processor, the memory, or the input/output circuit, further comprise:
a multiplexer coupled to an output of the non-volatile control cell, the multiplexer further including;
a first set of inputs coupled to outputs of the first set of storage cells;
a second set of inputs coupled to outputs of the second set of storage cells;
wherein the state of the non-volatile control cell configures the multiplexer to use either the first set of inputs or the second set of inputs; and
a multiplexer output configured to control the one or more operating parameters of the electronic system based on either the first set of inputs or the second set of inputs.

19. The electronic system of claim 13 , wherein at least one of the processor, the memory, or the input/output circuit further comprise:
an array of non-volatile memory cells including the first set of storage cells and the second set of storage cells; and
a control circuit coupled to the non-volatile control cell and configured to access the array based on the state of the non-volatile control cell, and to write values, based on information accessed from the array, into one or more registers, to program the one or more operating parameters of the electronic system.

20. The electronic system of claim 13 , wherein at least one of the processor, the memory, or the input/output circuit further comprise:
an array of non-volatile memory cells including the first set of storage cells and the second set of storage cells; and
address lines coupled to the array to control which memory cells of the array are accessed;
wherein a state of the non-volatile control cell determines a state of the address lines.

Assignees

• Intel Corp

Inventors

• Walker Julie M
• Rivers Doyle

Classifications

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C7/20 Primary

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title