Touch control detection system, delta-sigma modulator and modulating method thereof

Patent metadata

Field	Value
Publication number	US-2016126972-A1
Application number	US-201414582215-A
Country	US
Kind code	A1
Filing date	Dec 24, 2014
Priority date	Nov 3, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A touch control detection system, a delta-sigma modulator and a modulating method thereof are provided. The delta-sigma modulator includes a quantizer and N integrating units. The quantizer generates a modulating result signal. The integrating units are coupled in series. Each of the integrating receives an input signal, and each of the integrating units receives a plurality of gain parameters, N is a positive integer. The quantizer quantizes a signal on an output end of the N th stage integrating unit according to an error signal for generating the modulating result signal. A center frequency of a noise transfer function (NTF) of the delta-sigma modulator is adjusted according to the gain parameters, and the gain parameters are determined according to a frequency of the input signal.

First claim

What is claimed is:

1 . A delta-sigma modulator, comprising:
a quantizer, generating a modulating result signal; and N integrating units, coupled in series, the first stage integrating unit receiving an input signal, an output end of the N th stage integrating unit coupled to an input end of the quantizer, each of the integrating units receiving a plurality of gain parameters, and N being a positive integer, wherein, the quantizer quantizes a signal on the output end of the N th stage integrating unit according to an error signal for generating a modulating result signal, a center frequency of a noise transfer function of the delta-sigma modulator is adjusted according to the gain parameters for generating the modulating result signal, and the gain parameters are determined according to a frequency of the input signal.

2 . The delta-sigma modulator as recited in claim 1 , wherein each of the integrating units comprises:
a first buffer, adjusting a signal according to a first gain parameter for generating a first buffer signal; a first calculation unit, executing an arithmetic calculation on the first buffer signal, a second buffer signal and a third buffer signal for generating a first calculation result signal; a first integrator, receiving the first calculation result signal for performing an integration, so as to generate a first integration result signal; a second buffer, adjusting the modulating result signal according to a second gain parameter for generating the second buffer signal; a third buffer, adjusting a second integration result signal according to a third gain parameter for generating the third buffer signal; a fourth buffer, adjusting the first integration result signal according to a fourth gain parameter for generating a fourth buffer signal; a fifth buffer, adjusting the first integration result signal according to a fifth gain parameter for generating a fifth buffer signal; a second calculation unit, executing an arithmetic calculation on the fourth buffer signal and the fifth buffer signal for generating a second calculation result signal; and a second integrator, integrating the second calculation result signal to generate the second integration result signal, wherein the second integration result signal is provided to the next stage integrating unit or the quantizer.

3 . The delta-sigma modulator as recited in claim 2 , wherein the signal is the second integration result signal of the prior stage integrating unit or the input signal.

4 . The delta-sigma modulator as recited in claim 1 , further comprising:
a first buffer, adjusting the input signal according to a first gain parameter for generating a first buffer signal; and a first calculation unit, performing an arithmetic calculation on the first buffer signal and the signal on the output end of the N th stage integrating unit to generate an integration result signal, wherein each of the integrating units comprises:
a second buffer, adjusting the input signal according to a second gain parameter for generating a second buffer signal;
a third buffer, adjusting the modulating result signal according to a third gain parameter for generating a third buffer signal;
a second calculation unit, performing an arithmetic calculation on the second and the third buffer signals, a seventh buffer signal and an eighth buffer signal of the prior stage integrating unit to generate a first calculation result signal;
a first integrator, integrating the first calculation result signal to generate a first integration result signal;
a fourth buffer, adjusting the first integration result signal according to a fourth gain parameter for generating a fourth buffer signal;
a third calculation unit, performing arithmetic calculation on the fourth buffer signal, a fifth buffer signal and a sixth buffer signal to generate a second calculation result signal;
a fifth buffer, adjusting the input signal according to a fifth gain parameter for generating the fifth buffer signal;
a sixth buffer, adjusting the modulating result signal according to a sixth gain parameter for generating the sixth buffer signal;
a second integrator, integrating the second calculation result signal to generate a second integration result signal;
a seventh buffer, adjusting the second integration result signal according to a seventh gain parameter for generating the seventh buffer signal; and
an eighth buffer, adjusting the second integration result signal according to an eighth gain parameter for generating the eighth buffer signal,
wherein the eighth buffer signal is provided to the second calculation unit of the next stage integrating unit or the quantizer.

5 . The delta-sigma modulator as recited in claim 1 , further comprising:
a first buffer, adjusting the input signal according to a first gain parameter for generating a first buffer signal; and a first calculation unit, performing an arithmetic calculation on the first buffer signal and the fifth and the eighth buffer signals of each of the integrating units to generate the integration result signal; wherein each of the integrating units comprises:
a second buffer, adjusting the input signal according to a second gain parameter for generating a second buffer signal;
a third buffer, adjusting the modulating result signal or a second integration result signal of the prior stage integrating unit according to a third gain parameter for generating a third buffer signal;
a second calculation unit, performing an arithmetic calculation on the second and the third buffer signals and a seventh buffer signal to generate a first calculation result signal;
a first integrator, integrating the first calculation result signal to generate a first integration result signal;
a fourth buffer, adjusting the first integration result signal according to a fourth gain parameter for generating a fourth buffer signal;
a fifth buffer, adjusting the first integration result signal according to a fifth gain parameter for generating the fifth buffer signal;
a sixth buffer, adjusting the input signal according to a sixth gain parameter for generating the sixth buffer signal;
a third calculation unit, performing an arithmetic calculation on the fourth buffer signal and the sixth buffer signal to generate a second calculation result signal;
a second integrator, integrating the second calculation result signal to generate a second integration result signal;
a seventh buffer, adjusting the second integration result signal according to a seventh gain parameter for generating the seventh buffer signal; and
an eighth buffer, adjusting the second integration result signal according to a eighth gain parameter for generating the eighth buffer signal,
wherein the eighth buffer signal is provided to the second calculation unit of the next stage integrating units or the quantizer.

6 . The delta-sigma modulator as recited in claim 1 , wherein the quantizer comprises:
a calculation unit, performing an arithmetic calculation the signal on the output end of the N th stage integrating unit and the error signal so as to generate the modulating result signal.

7 . The delta-sigma modulator as recited in claim 6 , further comprising:
a digital-to-analog converter, converting the modulating result signal of analog format into digital format, and transmitting the modulating result signal of digital format to the integrating units.

8 . The delta-sigma modulator as recited in claim 1 , further comprising:
a gain parameter generator, receiving the input signal and generating the gain parameters according to a frequency of the input signal.

9 . A touch control detection system, comprising:
A touch sensor, generating a touch dete

Assignees

• Novatek Microelectronics Corp

Inventors

• Chang Chih-Yuan

Classifications

• H03M3/32 Primary

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M3/354

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error · CPC title

• G06F3/0416

  Control or interface arrangements specially adapted for digitisers · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/396 Primary

  among different frequency bands · CPC title