Voltage regulator

US10061337B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10061337-B2
Application numberUS-201615343485-A
CountryUS
Kind codeB2
Filing dateNov 4, 2016
Priority dateNov 4, 2015
Publication dateAug 28, 2018
Grant dateAug 28, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various embodiments provide a voltage regulator. The voltage regulator includes a supply voltage input to apply an input supply voltage, a supply voltage output to output an output supply voltage, and a first field effect transistor and a second field effect transistor, which are connected in series between the voltage supply input and the voltage supply output. The first field effect transistor has a higher operating voltage than the second field effect transistor. The voltage regulator further includes a regulator designed to set the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor to regulate the output supply voltage on the basis of a reference voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. A voltage regulator, comprising: a voltage supply input to apply an input supply voltage; a voltage supply output to output an output supply voltage; a first field effect transistor and a second field effect transistor, which are connected in series between the voltage supply input and the voltage supply output, wherein the first field effect transistor has a higher operating voltage than the second field effect transistor; and a regulator designed to set a gate voltage of the first field effect transistor and a gate voltage of the second field effect transistor to regulate the output supply voltage based on a reference voltage; wherein the regulator comprises a further field effect transistor, which is connected firstly to the gate of the first field effect transistor and the gate of the second field effect transistor and secondly to a low supply potential, and the regulator is designed to reduce the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor by means of opening the further field effect transistor. 2. The voltage regulator of claim 1 , wherein the first field effect transistor is a high-voltage transistor and the second field effect transistor is a low-voltage transistor. 3. The voltage regulator of claim 1 , wherein the first field effect transistor has a higher resistance than the second field effect transistor. 4. The voltage regulator of claim 1 , wherein the first field effect transistor has a higher gate oxide thickness than the second field effect transistor. 5. The voltage regulator of claim 1 , wherein the second field effect transistor has a larger channel width than the first field effect transistor. 6. The voltage regulator of claim 1 , wherein the second field effect transistor has a higher gain than the first field effect transistor. 7. The voltage regulator of claim 1 , wherein the first field effect transistor and the second field effect transistor form a cascode. 8. The voltage regulator of claim 1 , wherein the regulator is designed to regulate the output supply voltage to a desired voltage value. 9. The voltage regulator of claim 8 , wherein the desired voltage value is given by the reference voltage. 10. The voltage regulator of claim 1 , wherein the regulator is designed to increase the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor if the output supply voltage is lower than a desired voltage value, and to reduce the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor if the output supply voltage is higher than the desired voltage value. 11. The voltage regulator of claim 10 , wherein the regulator comprises a charge pump and is designed to increase the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor by means of the charge pump. 12. The voltage regulator of claim 1 , wherein the regulator comprises a comparator designed to compare the reference voltage with a comparison voltage representing the output supply voltage, and the regulator is designed to set the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor based on the result of the comparison. 13. The voltage regulator of claim 1 , further comprising: a voltage divider, which is connected to the voltage supply output and is designed to generate the comparison voltage from the output supply voltage. 14. The voltage regulator of claim 1 , wherein the gate of the first field effect transistor is coupled to an anode of a diode and the gate of the second field effect transistor is coupled to a cathode of the diode. 15. The voltage regulator of claim 14 , wherein the diode is implemented by means of a field effect transistor connected as a diode. 16. The voltage regulator of claim 1 , wherein the second field effect transistor is formed in a triple well structure. 17. The voltage regulator of claim 1 , wherein the first field effect transistor and the second field effect transistor are n-channel field effect transistors.

Assignees

Inventors

Classifications

  • G05F1/595Primary

    semiconductor devices connected in series · CPC title

  • using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

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Frequently asked questions

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What does patent US10061337B2 cover?
Various embodiments provide a voltage regulator. The voltage regulator includes a supply voltage input to apply an input supply voltage, a supply voltage output to output an output supply voltage, and a first field effect transistor and a second field effect transistor, which are connected in series between the voltage supply input and the voltage supply output. The first field effect transisto…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification G05F1/595. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 28 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).