Power-efficient, low-noise, and process/voltage/temperature (PVT)—insensitive regulator for a voltage-controlled oscillator (VCO)

Patent metadata

Field	Value
Publication number	US-9547324-B2
Application number	US-201414244321-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Apr 3, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Certain aspects of the present disclosure provide voltage regulating circuits which are power efficient, low noise, and substantially insensitive to changes in process technology, power supply voltage, and temperature. Such circuits may be used to provide the regulated voltage for a voltage-controlled oscillator (VCO), for example, as found in a radio frequency front end (RFFE). One example voltage regulating circuit generally includes a current source configured to supply or sink a reference current and a current mirror having a bias branch and a main branch, wherein the bias branch is connected with the current source, wherein the main branch includes a source follower to provide the regulated voltage, and wherein the reference current is available at a node for the regulated voltage.

First claim

What is claimed is:

1. A circuit for providing an output voltage, comprising:
a current source configured to supply or sink a reference current; and
a current mirror having a bias branch and a main branch, wherein the bias branch is connected with the current source, wherein the main branch includes a source follower to provide the output voltage at an output of the main branch, and wherein the output of the bias branch and an output of the main branch are coupled to an output of the circuit such that at least a portion of the reference current is combined with a branch current through the main branch and flows to the output of the circuit, wherein the current source is provided a first power supply voltage and the main branch of the current mirror is provided a second power supply voltage, wherein the first power supply voltage has a higher voltage than the second power supply voltage, and wherein the first power supply voltage and the second power supply voltage have higher voltages than the output voltage.

2. The circuit of claim 1 , wherein the bias branch comprises a first transistor, wherein the main branch comprises a second transistor, and wherein a gate of the first transistor is connected with a gate of the second transistor.

3. The circuit of claim 2 , wherein the bias branch comprises a third transistor connected in cascode with the first transistor, wherein the main branch comprises a fourth transistor connected in cascode with the second transistor, and wherein a gate of the third transistor is connected with a gate of the fourth transistor.

4. The circuit of claim 3 , wherein the gate of the third transistor is biased using a voltage divider, wherein the second power supply voltage is provided to the voltage divider.

5. The circuit of claim 3 , wherein the gate of the third transistor is connected with the gate of the fourth transistor via a first low pass filter and wherein the gate of the first transistor is connected with the gate of the second transistor via a second low pass filter.

6. The circuit of claim 3 , wherein a drain of the third transistor is connected with the current source and the gate of the first transistor, wherein a source of the third transistor is connected with a drain of the first transistor, and wherein a source of the first transistor is connected with the output of the circuit.

7. The circuit of claim 3 , wherein the second power supply voltage is provided to a drain of the fourth transistor, wherein a source of the fourth transistor is connected with a drain of the second transistor, and wherein a source of the second transistor is connected with the output of the circuit.

8. The circuit of claim 3 , wherein the first, second, third, and fourth transistors comprise n-channel metal-oxide semiconductor (NMOS) field-effect transistors.

9. The circuit of claim 2 , wherein a drain of the first transistor is connected with the gate of the first transistor.

10. The circuit of claim 1 , wherein the reference current and the branch current through the main branch compose a regulator current, and wherein the regulator current is substantially insensitive to variations in process technology, power supply voltage, and temperature.

11. The circuit of claim 1 , wherein the current source comprises a variable current source.

12. The circuit of claim 1 , wherein the current mirror comprises a low impedance current mirror.

13. The circuit of claim 1 , wherein the source follower comprises a p-channel metal-oxide semiconductor (PMOS) field-effect transistor.

14. A circuit for providing an output voltage, comprising:
a source follower configured to provide the output voltage and a regulated output current;
a current sensing circuit configured to generate a sensing current based on the regulated output current;
a current source configured to generate a reference current; and
a current mode comparator configured to compare the sensing current with the reference current and control a bias of the source follower based on the comparison, wherein a power supply voltage is provided to the source follower, the current sensing circuit, the current source, and the current mode comparator, wherein the source follower comprises a first transistor and a second transistor connected in series, wherein a gate of the first transistor is biased using a voltage divider configured to reduce a voltage of the power supply voltage.

15. The circuit of claim 14 , wherein the regulator current is substantially insensitive to variations in process technology, a voltage of the power supply voltage, and temperature.

16. The circuit of claim 14 , wherein a source of the first transistor is connected with a drain of the second transistor and wherein a source of the second transistor is connected with an output of the circuit.

17. The circuit of claim 16 , wherein an output of the current mode comparator is connected with a gate of the second transistor via a low pass filter.

18. The circuit of claim 17 , further comprising a switch in parallel with a resistor of the low pass filter, wherein the switch is closed during start-up of the circuit and wherein the switch is open during normal operation of the circuit.

19. The circuit of claim 14 , wherein the current sensing circuit comprises third, fourth, fifth, and sixth transistors connected in series.

20. The circuit of claim 19 , wherein the power supply voltage is provided to a drain of the third transistor, wherein a gate of the third transistor is connected with a gate of the first transistor, wherein a source of the third transistor is connected with a drain of the fourth transistor, wherein a gate of the fourth transistor is connected with a gate of the second transistor, wherein a source of the fourth transistor is connected with a drain of the fifth transistor, and wherein a source of the fifth transistor is connected with a drain of the sixth transistor.

21. The circuit of claim 20 , wherein the current sensing circuit comprises an amplifier having a negative input, a positive input, and an output, wherein the negative input is connected with an output of the circuit, wherein the positive input is connected with at least one of the source of the fourth transistor or the drain of the fifth transistor, and wherein the output of the amplifier is connected with a gate of the sixth transistor, such that the sensing current flows through the third, fourth, fifth, and sixth transistors.

22. The circuit of claim 21 , wherein a gate of the fifth transistor is biased by a bias voltage.

23. The circuit of claim 22 , wherein the gate of the fifth transistor is configured to be connected with an electrical ground for the power supply voltage during start-up of the circuit.

24. The circuit of claim 21 , wherein the current mode comparator comprises a seventh transistor and an eighth transistor connected in series, wherein a drain of the seventh transistor is connected with the current source and with the gate of the second transistor to form a feedback loop for controlling the bias of the source follower, wherein a gate of the seventh transistor is connected with a gate of the fifth transistor, wherein a source of the seventh transistor is connected with a drain of the eighth transistor, and wherein a gate of the eighth transistor is connected with a gate of the sixth transistor.

25. The circuit of claim 19 , wherein the first, second, third, fourth, fifth, and sixth transistors comprise n

Assignees

• Qualcomm Inc

Inventors

• Vahid Far Mohammad Bagher
• Komijani Abbas
• Park Chan Hong

Classifications

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• G05F3/02 Primary

  Regulating voltage or current · CPC title

• Y02D30/70

  in wireless communication networks · CPC title

• G05F1/595

  semiconductor devices connected in series · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title