Test circuits for integrated circuit counterfeit detection

US10060973B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10060973-B1
Application numberUS-201514719535-A
CountryUS
Kind codeB1
Filing dateMay 22, 2015
Priority dateMay 29, 2014
Publication dateAug 28, 2018
Grant dateAug 28, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit (IC) comprising: a main circuit that is configured to perform a predefined task; and a test circuit integrated with the main circuit in the IC that, when energized, is configured to emit an output signal that is indicative of a semiconductor fabrication facility where the IC was manufactured, the test circuit comprising a plurality of ring oscillator (RO) circuits, wherein the output signal is based upon signals emitted by each of the RO circuits, and further wherein each RO circuit in the plurality of RO circuits being non-identical to each other RO circuit in the plurality of RO circuits, the plurality of RO circuits comprising: a first RO circuit, the first RO circuit comprises a first trace of a first width; and a second RO circuit, the second RO circuit comprising a second trace of a second width, the first width being greater than the second width. 2. The IC of claim 1 , a third RO circuit in the plurality of RO circuits comprises a third trace formed of a first material, a fourth RO circuit in the plurality of RO circuits comprises a fourth trace formed of a second material, the first material being different from the second material. 3. The IC of claim 1 , a third RO circuit in the plurality of RO circuits comprises first transistors that each have a first dimension corresponding thereto, a fourth RO circuit in the plurality of RO circuits comprises second transistors that each have a second dimension corresponding thereto, the first dimension being larger than the second dimension. 4. The IC of claim 1 , the test circuit further comprises a switching circuit that is configured to independently electrically couple each RO circuit in the plurality of RO circuits with an energy source. 5. The IC of claim 1 , the output signal having a frequency content, the frequency content indicative of the semiconductor fabrication facility where the IC was manufactured. 6. An integrated circuit (IC) comprising: a main circuit that is configured to perform a predefined task; and a test circuit integrated with the main circuit in the IC that, when energized, is configured to emit an output signal that is indicative of a semiconductor fabrication facility where the IC was manufactured, the test circuit comprising a plurality of ring oscillator (RO) circuits, wherein the output signal is based upon signals emitted by each of the RO circuits, and further wherein each RO circuit in the plurality of RO circuits being non-identical to each other RO circuit in the plurality of RO circuits, the plurality of RO circuits comprising: a first RO circuit, the first RO circuit comprises a first trace formed of a first material; and a second RO circuit, the second RO circuit comprises a second trace formed of a second material, the first material being different from the second material. 7. The IC of claim 6 , the plurality of RO circuits further comprising: a third RO circuit, the third RO circuit comprises a first trace of a first width; and a fourth RO circuit, the fourth RO circuit comprising a second trace of a second width, the first width being greater than the second width. 8. The IC of claim 6 , a third RO circuit in the plurality of RO circuits comprises first transistors that each have a first dimension corresponding thereto, a fourth RO circuit in the plurality of RO circuits comprises second transistors that each have a second dimension corresponding thereto, the first dimension being larger than the second dimension. 9. The IC of claim 6 , the test circuit further comprises a switching circuit that is configured to independently electrically couple each RO circuit in the plurality of RO circuits with an energy source. 10. The IC of claim 6 , the output signal having a frequency content, the frequency content indicative of the semiconductor fabrication facility where the IC was manufactured. 11. An integrated circuit (IC) comprising: a main circuit that is configured to perform a predefined task; and a test circuit integrated with the main circuit in the IC that, when energized, is configured to emit an output signal that is indicative of a semiconductor fabrication facility where the IC was manufactured, the test circuit comprising a plurality of ring oscillator (RO) circuits, wherein the output signal is based upon signals emitted by each of the RO circuits, and further wherein each RO circuit in the plurality of RO circuits being non-identical to each other RO circuit in the plurality of RO circuits, the plurality of RO circuits comprising: a first RO circuit, the first RO circuit comprising first transistors that each have a first dimension corresponding thereto; and a second RO circuit, the second RO circuit comprising second transistors that each have a second dimension corresponding thereto, the first dimension being larger than the second dimension. 12. The IC of claim 11 , the plurality of RO circuits further comprising: a third RO circuit, the third RO circuit comprises a first trace of a first width; and a fourth RO circuit, the fourth RO circuit comprising a second trace of a second width, the first width being greater than the second width. 13. The IC of claim 11 , a third RO circuit in the plurality of RO circuits comprises a third trace formed of a first material, a fourth RO circuit in the plurality of RO circuits comprises a fourth trace formed of a second material, the first material being different from the second material. 14. The IC of claim 11 , the test circuit further comprises a switching circuit that is configured to independently electrically couple each RO circuit in the plurality of RO circuits with an energy source. 15. The IC of claim 11 , the output signal having a frequency content, the frequency content indicative of the semiconductor fabrication facility where the IC was manufactured.

Assignees

Inventors

Classifications

  • Modifications for increasing the reliability {for protection} · CPC title

  • Analysis of signal quality (G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20) · CPC title

  • involving digital signatures · CPC title

  • Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title

  • using group based signatures, e.g. ring or threshold signatures · CPC title

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What does patent US10060973B1 cover?
Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicati…
Who is the assignee on this patent?
National Tech And Engineering Solutions Of Sandia Llc, Nat Tech & Eng Solutions Sandia Llc
What technology area does this patent fall under?
Primary CPC classification G01R31/2894. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 28 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).