Method of processing a semiconductor structure

Patent metadata

Field	Value
Publication number	US-10056531-B2
Application number	US-201214238477-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Aug 26, 2011
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A method according to embodiments of the invention includes providing a wafer including a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a III-nitride light emitting layer sandwiched between an n-type region and a p-type region. The wafer is bonded to a second substrate. The growth substrate is removed. After bonding the wafer to the second substrate, the wafer is processed into multiple light emitting devices.

First claim

What is being claimed is:

1. A method comprising:
providing a wafer comprising a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a III-nitride light emitting layer sandwiched between an n-type region and a p-type region;
bonding the wafer to a transparent substrate that comprises a wavelength converting material disposed in glass;
removing the growth substrate;
after bonding the wafer to the transparent substrate, processing the wafer into multiple light emitting devices;
testing the wafer after processing the wafer into multiple light emitting devices and before dicing the wafer; and
adjusting an amount of wavelength converting material corresponding to each light emitting device according to the results of the testing.

2. The method of claim 1 wherein adjusting comprises removing wavelength converting material by laser ablation.

3. The method of claim 1 wherein adjusting comprises adding wavelength converting material.

4. The method of claim 1 wherein bonding the wafer to a second substrate comprises pressing the wafer and the second substrate together at a temperature greater than 500° C.

5. The method of claim 1 wherein processing the wafer into multiple light emitting devices comprises:
forming a metal contact on the p-type region;
removing a portion of the light emitting layer and the p-type region to reveal a portion of the n-type region; and
forming a metal contact on the n-type region exposed by removing a portion of the light emitting layer and the p-type region.

6. The method of claim 1 wherein processing the wafer into multiple light emitting devices comprises dicing the wafer into single light emitting diodes or groups of light emitting diodes.

7. A method comprising:
providing a wafer comprising a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a III-nitride light emitting layer sandwiched between an n-type region and a p-type region;
bonding, using a bonding material, the wafer to a transparent substrate that comprises a wavelength converting material disposed in glass;
removing the growth substrate; and
after bonding the wafer to the second substrate, processing the wafer into multiple light emitting devices.

8. The method of claim 1 further comprising forming an optical impedance matching layer on the semiconductor structure prior to bonding.

9. The method of claim 1 further comprising texturing a surface of the second substrate opposite a surface bonded to the semiconductor structure.

10. The method of claim 1 wherein processing the wafer into multiple light emitting devices occurs after removing the growth substrate.

11. The method of claim 1 further comprising bonding the wafer to a handle before removing the growth substrate, wherein bonding the wafer to a second substrate occurs after removing the growth substrate while the semiconductor structure is bonded to the handle.

12. The method of claim 1 further comprising forming a reflective contact on a surface of the semiconductor structure opposite a surface bonded to the second substrate.

Assignees

• Bhat Jerome Chandra
• Steigerwald Daniel Alexander
• Camras Michael David
• Choi Han Ho
• Gardner Nathan Fredrick
• Shchekin Oleg Borisovich
• Lumileds Llc

Inventors

• Bhat Jerome Chandra
• Steigerwald Daniel Alexander
• Camras Michael David
• Choi Han Ho
• Gardner Nathan Fredrick
• Shchekin Oleg Borisovich

Classifications

• H10P74/235

  comprising optical enhancement of defects or not-directly-visible states · CPC title

• H01L33/501

  Electricity · mapped topic

• H01L2933/0041

  Electricity · mapped topic

• H01L22/24

  Electricity · mapped topic

• H01L33/0079

  Electricity · mapped topic