Transistors comprising doped region-gap-doped region structures and methods of fabrication

Patent metadata

Field	Value
Publication number	US-9368591-B2
Application number	US-201414334950-A
Country	US
Kind code	B2
Filing date	Jul 18, 2014
Priority date	Jul 18, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming a plurality of doped regions in a semiconductor channel disposed on a semiconductor substrate, wherein the plurality of doped regions are formed adjacent to a dummy gate disposed on a dummy gate oxide, the dummy gate oxide disposed on the semiconductor substrate;
forming a plurality of dummy spacers, wherein the plurality of dummy spacers are disposed adjacent to the dummy gate;
forming a plurality of source/drain regions adjacent to the dummy gate;
depositing a dielectric layer over the source/drain regions;
removing the dummy gate to form a gate cavity;
removing the plurality of dummy spacers;
depositing a final spacer layer after removing the plurality of dummy spacers;
performing an etch of the final spacer layer to form final spacers;
removing the dummy gate oxide after performing the etch of the final spacer layer; and
forming a metal gate in the gate cavity.

2. The method of claim 1 , further comprising forming a silicon nitride gate cap on the metal gate.

3. The method of claim 1 , wherein forming the plurality of source/drain regions comprises forming epitaxial silicon regions.

4. The method of claim 1 , wherein forming the plurality of source/drain regions comprises forming epitaxial silicon germanium regions.

5. The method of claim 1 , wherein removing the dummy gate oxide is performed with a chemical oxide removal process.

6. The method of claim 1 , wherein removing the dummy gate oxide is performed with a Siconi process.

7. The method of claim 1 , wherein depositing the final spacer layer is performed with an atomic layer deposition process.

8. The method of claim 1 , wherein depositing the final spacer layer comprises depositing at least one of SiBCN and SiOCN.

Assignees

• Globalfoundries Inc
• IBM

Inventors

• Bentley Steven J
• Jacob Ajey Poovannummoottil
• Chen Chia-Yu
• Yamashita Tenko

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title